Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.8.2. Differential I/O Standards Support

Table 38.  Differential I/O Standards Support in Intel® Cyclone® 10 LP I/O Banks
I/O Standard I/O Bank External Resistor at Transmitter TX RX
LVDS 1, 2, 5, 6 Not required Yes Yes
All Three resistors
RSDS 1, 2, 5, 6 Not required Yes
3, 4, 7, 8 Three resistors
All Single resistor
Mini-LVDS 1, 2, 5, 6 Not required Yes
All Three resistors
PPDS 1, 2, 5, 6 Not required Yes
All Three resistors
Bus LVDS All Single resistor Yes Yes
Differential LVPECL All Yes
Differential SSTL-2 All Yes Yes
Differential SSTL-18 All Yes Yes
Differential 1.8 V HSTL All Yes Yes
Differential 1.5 V HSTL All Yes Yes
Differential 1.2 V HSTL All Yes Yes

The following conditions apply to the differential I/O standard support:

  • The Bus LVDS transmitter and receiver fMAX depend on system topology and performance requirement.
  • The Differential LVPECL I/O standard is supported only on dedicated clock input pins.
  • The following differential I/O standards are supported only on clock input pins and PLL clock output pins:
    • Differential SSTL-2 and Differential SSTL-18
    • Differential 1.8 V HSTL, Differential 1.5 V HSTL, and Differential 1.2 V HSTL
  • PLL clock output pins do not support Class II interface for these differential I/O standards:
    • Differential SSTL-18
    • Differential 1.8 V HSTL, Differential 1.5 V HSTL, and Differential 1.2 V HSTL
  • Differential 1.2 V HSTL Class II I/O standard is supported only in column I/O banks.

Did you find the information on this page useful?

Characters remaining:

Feedback Message