Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
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5.7.3.1. OCT Calibration

The OCT calibration circuit compares the total impedance of the output buffer to the external resistors connected to the RUP and RDN pins. The circuit dynamically adjusts the output buffer impedance until it matches the external resisters.

In Intel® Cyclone® 10 LP devices, there is one OCT calibration block on each side of the device. The calibration block supports both I/O banks on the side on which it is located:

  • If you enable OCT calibration for both I/O banks on the same device side, use the same VCCIO on both banks.
  • If the VCCIO values of the I/O banks on the same side are not the same, you can use OCT calibration only on the I/O bank that contains the calibration block.

Each OCT calibration block comes with a pair of RUP and RDN pins. During calibration, the RUP and RDN pins are each connected through an external 25 Ω ±1% or 50 Ω ±1% resistor for respective on-chip series termination value of 25 Ω or 50 Ω:

  • RUP—connected to VCCIO.
  • RDN—connected to GND.
Figure 71. RS OCT with Calibration SetupThis figure shows the external calibration resistors setup on the RUP and RDN pins and the associated OCT calibration circuitry.


The OCT calibration circuit compares the external resistors to the internal resistance using comparators. The OCT calibration block uses the comparators' output to dynamically adjust buffer impedance.

During calibration, the resistance of the RUP and RDN pins varies. To estimate of the maximum possible current through the external calibration resistors, assume a minimum resistance of 0 Ω on the RUP and RDN pins.

The RUP and RDN pins go to a tri-state condition when calibration is completed or not running. These two pins are dual-purpose I/Os and function as regular I/Os if you do not use the calibration circuit.