Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents
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6.1.1. Active Serial (AS) Configuration

Figure 82. High-Level Overview of Serial Configuration Device Programming for the Active Serial Configuration Scheme

In the AS configuration scheme, configuration data is stored in a serial configuration device. These devices are low-cost devices with non-volatile memories that feature a simple four-pin interface and a small form factor.

The four-pin interface consists of these pins:
  • Serial clock input (DCLK)
  • Serial data output (DATA1(DATA))
  • Active-low chip select (nCS)
  • AS data input (DATA0(ASDI))

Serial configuration devices provide a serial interface to access the configuration data. During device configuration, Intel® Cyclone® 10 LP devices read the configuration data through the serial interface, decompress the data if necessary, and configure their SRAM cells.

In this scheme, the Intel® Cyclone® 10 LP device controls the configuration interface. To gain control of the serial configuration device pins, hold the nCONFIG pin low and pull the nCE pin high to cause the device to reset and tri-state the AS configuration pins.

AS Configuration Guidelines

Consider the following guidelines when you configure the Intel® Cyclone® 10 LP devices:

  • Connect the pull-up resistors of the FPGA device to the VCC supply of the bank in which the pin resides.
  • You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
  • The MSEL pin settings vary for different configuration voltage standards and POR time.
  • The nCSO and ASDO pins are dual-purpose I/O pins. The ASDO pin also functions as the DATA[1] pin in FPP mode.
  • For multi-device configurations, connect the pull-up resistor of the slave FPGA device(s) to the VCCIO supply voltage of I/O bank in which the nCE pin resides.
  • Connect the repeater buffers between the master and slave devices of the FPGA device for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation.
  • The 50 Ω series resistors are optional if the 3.3 V configuration voltage standard is applied. For optimal signal integrity, connect these 50 Ω series resistors if the 3.0 V configuration voltage standard is applied.