Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.3.1.6. FIFO IP Core References

The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.

  • Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to implement single- and dual-clock FIFO buffers in your design.
  • Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain.
  • The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Figure 27.  FIFO IP Core: SCFIFO Mode Signals
Figure 28. FIFO IP Core: DCFIFO Mode Signals

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