Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.1. PLL Features

Table 17.   Intel® Cyclone® 10 LP PLL Features
Feature Support
C output counters 5
M, N, C counter sizes 1 to 512 8
Dedicated clock outputs 1 single-ended or 1 differential
Dedicated clock input pins 4 single-ended or 2 differential
Spread-spectrum input clock tracking Yes 9
PLL cascading Through GCLK
Source synchronous compensation Yes
No compensation mode Yes
Normal compensation Yes
Zero-delay buffer compensation Yes
Phase shift resolution Down to 96 ps increments 10
Programmable duty cycle Yes
Output counter cascading Yes
Input clock switchover Yes
User mode reconfiguration Yes
Loss of lock detection Yes
8 C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 256.
9 Only applicable if the input clock jitter is in the input jitter tolerance specifications.
10 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Intel® Cyclone® 10 LP devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.

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