Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.1.6. Clock Enable Signals

Intel® Cyclone® 10 LP devices support clkena signals at the GCLK network level. This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the output clock, the PLL does not need a resynchronization or re-lock period because the circuit gates off the clock at the clock network level. In addition, the PLL can remain locked independent of the clkena signals because the loop-related counters are not affected.

Figure 40. clkena ImplementationThis figure shows the implementation of the clkena signal with a single register. The clkena circuitry controlling the output C0 of the PLL to an output pin is implemented with two registers instead of a single register.
Figure 41. Example Waveform of clkena Implementation with Output EnableThis figure shows the waveform example for a clock output enable. The clkena signal is sampled on the falling edge of the clock (clkin). This feature is useful for applications that require low power or sleep mode.

The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization.

Intel recommends using the clkena signals when switching the clock source to the PLLs or the GCLK. The recommended sequence is:

  1. Disable the primary output clock by de-asserting the clkena signal.
  2. Switch to the secondary clock using the dynamic select signals of the clock control block.
  3. Allow some clock cycles of the secondary clock to pass before reasserting the clkena signal. The exact number of clock cycles you must wait before enabling the secondary clock is design-dependent. You can build custom logic to ensure glitch-free transition when switching between different clock sources.

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