Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices

Intel® Cyclone® 10 LP devices offer highly configurable GPIOs with these features:

  • Support for various single-ended and differential I/O standards.
  • Programmable current strength, bus hold, pull-up resistors, and delays.
  • Programmable slew rate control to optimize signal integrity.
  • Optional open-drain output for each I/O pin.
  • True and emulated LVDS buffers with LVDS SERDES implemented using logic elements in the device core.
  • Programmable pre-emphasis for the true LVDS output buffers.
  • Calibrated on-chip series termination (RS OCT) or driver impedance matching (RS) for single-endd I/O standards.
  • Support for hot socketing implementation.

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