Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.2. Intel® Cyclone® 10 LP Embedded Memory General Features

Intel® Cyclone® 10 LP embedded memory supports the following general features:

  • 8,192 memory bits per block (9,216 bits per block including parity).
  • Independent read-enable (rden) and write-enable (wren) signals for each port.
  • Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
  • Variable port configurations.
  • Single-port and simple dual-port modes support for all port widths.
  • True dual-port (one read and one write, two reads, or two writes) operation.
  • Byte enables for data input masking during writes.
  • Two clock-enable control signals for each port (port A and port B).
  • Initialization file to preload memory content in RAM and ROM modes.

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