Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.3.4. Device Configuration Pins

Table 46.  Configuration Pins Summary for Intel® Cyclone® 10 LP Devices
Bank Configuration Pin Dedicated Input/Output Powered By Configuration Mode
1 nCSO Output VCCIO AS
6 CRC_ERR0R Output VCCIO/Pull-up Optional, all modes
1 DATA[0] Input VCCIO PS, FPP, AS
1 DATA[1]/ASDO Input VCCIO FPP
Output VCCIO AS
8 DATA[7..2] Input VCCIO FPP
6 INIT_DONE Output Pull-up Optional, all modes
1 nSTATUS Yes Bidirectional Pull-up All modes
1 nCE Yes Input VCCIO All modes
1 DCLK Yes Input VCCIO PS, FPP
Output VCCIO AS
6 CONF_DONE Yes Bidirectional All modes
1 TDI Yes Input VCCIO JTAG
1 TMS Yes Input VCCIO JTAG
1 TCK Yes Input VCCIO JTAG
1 nCONFIG Yes Input VCCIO All modes
6 CLKUSR Input VCCIO Optional
6 nCEO Output VCCIO Optional, all modes
6 MSEL[] Yes Input VCCINT All modes
1 TDO Yes Output VCCIO JTAG
5 DEV_CLRn Input VCCIO Optional
5 DEV_OE Input VCCIO Optional

To tri-state AS configuration pins in the AS configuration scheme, turn on the Enable input tri-state on active configuration pins in user mode option from the Device and Pin Options dialog box. This tri-states DCLK, nCSO, Data[0], and Data[1]/ASDO pins.

Dual-purpose pins settings for these pins are ignored. To set these pins to different settings, turn off the Enable input tri-state on active configuration pins in user mode option and set the desired setting from the Dual-purpose Pins Setting menu.

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