Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents

2.2.1. Control Signals

The clock-enable control signal controls the clock entering the input and output registers and the entire M9K memory block. This signal disables the clock so that the M9K memory block does not see any clock edges and does not perform any operations.

The rden and wren control signals control the read and write operations for each port of the M9K memory blocks. You can disable the rden or wren signals independently to save power whenever the operation is not required.

Figure 7. Register Clock, Clear, and Control Signals Implementation in M9K Embedded Memory Block