Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

8.2. I/O Voltage Support in the JTAG Chain

An Intel® Cyclone® 10 LP device operating in BST mode uses four required pins—TDI, TDO, TMS, and TCK. The TDO output pin and all JTAG input pins are powered by the VCCIO power supply of I/O Bank 1 .

The TDO pin of a device drives out at the voltage level according to the VCCIO of the device. The devices can interface with each other although the devices may have different VCCIO levels.

For example, a device with 3.3-V VCCIO can drive a device with 5.0-V VCCIO because 3.3 V meets the minimum VIH on transistor-to-transistor logic (TTL)-level input for the 5.0-V VCCIO device.

For multiple devices in a JTAG chain with the 3.0-V/3.3-V I/O standard, you must connect a 25-Ω series resistor on a TDO pin driving a TDI pin.

To interface the TDI and TDO lines of the JTAG pins of devices that have different VCCIO levels, insert a level shifter between the devices. If possible, construct the JTAG chain where device with a higher VCCIO level drives to a device with an equal or lower VCCIO level. In this setup, you only require a level shifter for shifting the TDO level to a level JTAG tester accept.

Figure 111. JTAG Chain of Mixed Voltages and Level Shifters

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