Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

9.2.2. I/O Pins Remain Tri-stated During Power Up

The output buffers of the Intel® Cyclone® 10 LP device are turned off during system power up or power down. The Intel® Cyclone® 10 LP device family does not drive out until the device is configured and working in recommended operating conditions. The I/O pins are tristated during power up or power down.

Note: The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration. The weak pull-up resistors are not enabled prior to POR.

A possible concern for semiconductor devices in general regarding hot-socketing is the potential for latch up. Latch up can occur when electrical subsystems are hot-socketed into an active system. During hot-socketing, the signal pins may be connected and driven by the active system. This occurs before the power supply can provide current to the VCC of the device and ground planes. This condition can lead to latch up and cause a low-impedance path from VCC to ground in the device. As a result, the device extends a large amount of current, possibly causing electrical damage.

The design of the I/O buffers and hot-socketing circuitry ensures that the Intel® Cyclone® 10 LP device family is immune to latch up during hot-socketing.