Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Document Table of Contents

5.7.3. Intel® Cyclone® 10 LP On-Chip I/O Termination

The on-chip termination (OCT) block in Intel® Cyclone® 10 LP devices provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs.

The devices support driver impedance matching to match the impedance of the transmission line, which is typically 25 Ω or 50 Ω. Impedance matching uses the capabilities of the output driver and is subject to a certain degree of variation, depending on the process, voltage, and temperature.

Table 36.  OCT Schemes Supported in Intel® Cyclone® 10 LP Devices
Direction OCT Schemes I/O Bank Support
Output RS OCT with calibration Top, bottom, and right I/O banks
RS OCT without calibration All I/O banks

The Intel® Cyclone® 10 LP devices support serial (RS) OCT for single-ended output pins and bidirectional pins.

  • For bidirectional pins, OCT is active for output only.
  • VCCIO and VREF must be compatible for all I/O pins to enable RS OCT in an I/O bank.
  • I/O standards that support different RS values can reside in the same I/O bank if their VCCIO and VREF do not conflict.
  • Dedicated configuration pins and JTAG pins do not support impedance matching or series termination.
Figure 69. RS OCT with Calibration in Intel® Cyclone® 10 LP DevicesIn this figure, the RS is the intrinsic impedance of the transistors that make up the I/O buffer.

Figure 70. RS OCT without Calibration in Intel® Cyclone® 10 LP DevicesIn this figure, the RS is the intrinsic transistor impedance.

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