Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents

4.1.3. Clock Control Block

The clock control block drives the GCLKs. Clock control blocks are located on each side of the device, close to the dedicated clock input pins. GCLKs are optimized for minimum clock skew and delay.

Table 16.  Clock Control Block Inputs
Input Description
Dedicated clock input pins Dedicated clock input pins can drive clocks or global signals, such as synchronous and asynchronous clears, presets, or clock enables onto given GCLKs.
Dual-purpose clock (DPCLK and CDPCLK) I/O input DPCLK and CDPCLK pins are bidirectional dual function pins that are used for high fan-out control signals, such as protocol signals, TRDY and IRDY signals for PCI via the GCLK. Clock control blocks that have inputs driven by dual-purpose clock I/O pins cannot drive PLL inputs.
PLL outputs PLL counter outputs can drive the GCLK.
Internal logic You can drive the GCLK through logic array routing to enable the internal logic elements (LEs) to drive a high fan-out, low-skew signal path. Clock control blocks that have inputs driven by internal logic cannot drive PLL inputs.

In Intel® Cyclone® 10 LP devices, dedicated clock input pins, PLL counter outputs, dual-purpose clock I/O inputs, and internal logic can all feed the clock control block for each GCLK. The output from the clock control block in turn feeds the corresponding GCLK. The GCLK can drive the PLL input if the clock control block inputs are outputs of another PLL or dedicated clock input pins.

The maximum number of clock control blocks per Intel® Cyclone® 10 LP device is 20.

The control block has two functions:

  • Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK, and internal logic input)
  • GCLK network power down (dynamic enable and disable)
Figure 37. Clock Control BlockEach PLL generates five clock outputs through the c[4..0] counters. Two of these clocks can drive the GCLK through a clock control block.