Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.8.1. High-Speed Differential I/O Interface

The Intel® Cyclone® 10 LP devices support LVDS, RSDS, mini-LVDS, and PPDS high-speed differential I/O standards.

Differential Input

The Intel® Cyclone® 10 LP devices features true input buffers for these I/O standards on the top, bottom, and right I/O banks.

Differential Output

The Intel® Cyclone® 10 LP devices features dedicated differential output buffers:

  • The true output drivers are available on the row I/O banks.
  • Some of the differential pin pairs (p and n pins) are not located on adjacent pins. In these cases, a power pin is located between the p and n pins.

The Intel® Cyclone® 10 LP devices provide emulated support for these I/O standards on all columns and row I/O banks:

  • Emulated differential output uses a pair of single-ended output pins.
  • In the pin pair, the second output pin is programmed as inverted.
  • The emulated differential output requires an external resistor network.

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