Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

5.9.7. Guideline: Board Design for Signal Quality

Consider the critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques to get the best performance from Intel® Cyclone® 10 LP devices.

Use the following general guidelines to improve signal quality:

  • Base board designs on controlled differential impedance. Calculate and compare all parameters, such as trace width, trace thickness, and the distance between two differential traces.
  • Maintain equal distance between traces in differential I/O standard pairs as much as possible. Routing the pair of traces close to each other maximizes the common-mode rejection ratio (CMRR).
  • Longer traces have more inductance and capacitance. These traces must be as short as possible to limit signal integrity issues.
  • Place termination resistors as close to receiver input pins as possible.
  • Use surface mount components.
  • Avoid 90° corners on board traces.
  • Use high-performance connectors.
  • Design backplane and card traces so that trace impedance matches the impedance of the connector and termination.
  • Keep an equal number of vias for both signal traces.
  • Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the TCCS value increases.
  • Limit vias because they cause discontinuities.
  • Keep switching transistor-to-transistor logic (TTL) signals away from differential signals to avoid possible noise coupling.
  • Do not route TTL clock signals to areas under or above the differential signals.
  • Analyze system-level signals.