Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Document Table of Contents Configuring the Device

In the second stage, the SFL design in the master device enables you to write the configuration data for the device chain into the serial configuration device with the Intel® Cyclone® 10 LP device JTAG interface.

The JTAG interface sends the programming data for the serial configuration device to the Intel® Cyclone® 10 LP device first. The Intel® Cyclone® 10 LP device then uses the ASMI pins to send the data to the serial configuration device.

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