1.1.1. LE Features
Each LE input is directed to different destinations to implement the desired logic function. In both the normal or arithmetic operating modes of the LE, there are six available inputs:
- Four data inputs from the LAB local interconnect
- One LE carry-in from the previous LE carry-chain
- One register chain connection
Each LE has three general routing outputs:
- Two LE outputs drive the column or row and direct link routing connections
- One LE output drives the local interconnect resources
Intel® Cyclone® 10 LP devices support register packing. With register packing, the LUT or register output drives the three outputs independently. This feature improves device utilization by using the register and the LUT for unrelated functions.
The LAB-wide synchronous load control signal is not available if you use register packing.
Register Chain Output
Each LE has a register chain output that allows registers in the same LAB to cascade together. This feature speeds up connections between LABs and optimizes local interconnect resources:
- LUTs are used for combinational functions
- Registers are used for an unrelated shift register implementation
You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation. Each register has the following inputs:
- Clock—driven by signals that use the global clock network, general-purpose I/O pins, or internal logic
- Clear—driven by signals that use the global clock network, general-purpose I/O pins, or internal logic
- Clock enable—driven by the general-purpose I/O pins or internal logic
For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs.
The register feedback mode allows the register output to feed back into the LUT of the same LE. Register feedback ensures that the register is packed with its own fan-out LUT, providing another mechanism for improving fitting. The LE can also drive out registered and unregistered versions of the LUT output.
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