Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.5.4.1. Control Register

The remote system upgrade control register stores the application configuration address, the user watchdog timer settings, and option bits for an application configuration.

Table 48.  Control Register Bits
Bit Name Value Description
11–0 Wd_timer[11..0] 12'b000000000000 User watchdog time-out value; most significant 12 bits of 29-bit count value: {Wd_timer[11..0],17'b1000}.
33–12 Ru_address[21..0] 22'b0000000000000000000000 Configuration address time-out value; most significant 22 bits of 24-bit boot address value: boot_address[23:0] = {Ru_address[21..0],2'b0}.
34 Rsv1 1'b0 Reserved bit
35 Wd_en 1'b1 User watchdog timer enable bit. Set this bit to 1 to enable the watchdog timer.
36 Osc_int 1'b1 Internal oscillator as startup state machine clock enable bit. Option bit for the application configuration.

This bit ensures a functional startup clock to eliminate the hanging of start up.

Note: When all option bits are turned on, they provide complete coverage for the programming and startup portions of the application configuration. Intel recommends turning on both the Osc_int and Cd_early option bits.
37 Cd_early 1'b1 Early CONF_DONE check. Option bit for the application configuration.
When enabled, this option bit ensures that there is a valid configuration at the boot address specified by the factory configuration and that it is of the proper size. If an invalid configuration is detected or the CONF_DONE pin asserts too early, the device resets and then reconfigures the factory configuration image.
Note: When all option bits are turned on, they provide complete coverage for the programming and startup portions of the application configuration. Intel recommends turning on both the Osc_int and Cd_early option bits.
38 Rsv2 1'b1 Reserved bit

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