Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

1.2.2. LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs.

The control signals include:

  • Two clock signals
  • Two clock enable signals
  • Two asynchronous clear signals
  • One synchronous clear signal
  • One synchronous load signal
Figure 6. LAB-Wide Control Signals for Intel® Cyclone® 10 LP Devices
Table 1.  Control Signal Descriptions for Intel® Cyclone® 10 LP Devices
Control Signal Description
labclk1
  • Each LAB can use two clocks signals. The clock and clock enable signals of each LAB are linked. For example, any LE in a particular LAB using the labclk1 signal also uses the labclkena1 signal.
  • If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals.
  • The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide clock signals. The MultiTrack interconnect inherent low skew allows clock and control signal distribution in addition to data distribution.
labclk2
labclkena1
  • Each LAB can use two clock enable signals. The clock and clock enable signals of each LAB are linked. For example, any LE in a particular LAB using the labclk1 signal also uses the labclkena1 signal.
  • Deasserting the clock enable signal turns off the LAB-wide clock signal.
labclkena2
labclr1 Asynchronous clear signals:
  • LAB-wide control signals that control the logic for the clear signal of the register.
  • The LE directly supports an asynchronous clear function.
labclr2
syncload Synchronous load and synchronous clear signals:
  • Can be used for implementing counters and other functions
  • LAB-wide control signals that affect all registers in the LAB
synclr

You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously.

Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals.

An LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. Intel® Cyclone® 10 LP devices only support either a preset or asynchronous clear signal.

In addition to the clear port, Intel® Cyclone® 10 LP devices provide a chip-wide reset pin (DEV_CLRn) to reset all registers in the device. An option set before compilation in the Intel® Quartus® Prime software controls this pin. This chip-wide reset overrides all other control signals.

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