Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.1.4.6.1. Loading the SFL Design

The intelligent host uses the JTAG interface to configure the master device with an SFL design.

The SFL design bridges the JTAG interface and AS interface with glue logic. The SFL design allows the master device to control the access of four serial configuration device pins or Active Serial Memory Interface (ASMI) pins, through the JTAG interface. The ASMI pins are serial clock input (DCLK), serial data output (DATA), AS data input (ASDI), and active-low chip select (nCS) pins.

If you configure a master device with an SFL design, the master device enters user mode even though the slave devices in the multiple device chain are not being configured. The master device enters user mode with a SFL design even though the CONF_DONE signal is externally held low by the other slave devices in chain.

Figure 100. Programming Serial Configuration Devices In-System Using the JTAG Interface

Did you find the information on this page useful?

Characters remaining:

Feedback Message