Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.1.4. GCLK Network Clock Source Generation

Figure 38. Clock Networks and Clock Control Block Locations in Intel® Cyclone® 10 LP Devices

The inputs to the five clock control blocks on each side of the Intel® Cyclone® 10 LP device must be chosen from among the following clock sources:

  • Three or four clock input pins, depending on the specific device
  • Five PLL counter outputs
  • Two DPCLK pins and two CDPCLK pins from both the left and right sides and four DPCLK pins from both the top and bottom
  • Five signals from internal logic

From the clock sources listed above, only two clock input pins, two PLL clock outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into any given clock control block.

Out of these six inputs to any clock control block, the two clock input pins and two PLL outputs are dynamically selected to feed a GCLK. The clock control block supports static selection of the signal from internal logic.

Figure 39. Clock Control Blocks on Each Side of Intel® Cyclone® 10 LP DeviceThe left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.

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