Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices

This chapter describes the hierarchical clock networks and phase-locked loops (PLLs) with advanced features in the Intel® Cyclone® 10 LP devices. It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time, allowing you to sweep PLL output frequencies and dynamically adjust the output clock phase shift.

The Intel® Quartus® Prime software enables the PLLs and their features without external devices.

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