Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.12. PLL Cascading

Two PLLs are cascaded to each other through the clock network. If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting.

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