Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.5.5. Remote System Upgrade State Machine

The remote system upgrade control and update registers have identical bit definitions but serve different functions.

Both registers can only be updated when the device is loaded with a factory configuration image. However, the user logic controls the update register writes and the remote system upgrade state machine controls the control register writes.

In factory configurations, the user logic should send the option bits (Cd_early and Osc_int), the configuration address, and watchdog timer settings for the next application configuration bit to the update register. When the logic array configuration reset (RU_nCONFIG) goes high, the remote system upgrade state machine updates the control register with the contents of the update register and starts system reconfiguration from the new application page.
Note: To ensure the successful reconfiguration between the pages, assert the RU_nCONFIG signal for a minimum of 250 ns. This is equivalent to strobing the reconfig input of the Altera Remote Update IP core high for a minimum of 250 ns.

If there is an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (based on mode and error condition) by setting the control register accordingly.

The remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition, but before the factory configuration is loaded.

Table 51.  Control Register Contents After an Error or Reconfiguration Trigger ConditionThe table below lists the contents of the control register after such an event occurs for all possible error or trigger conditions.
Reconfiguration Error/Trigger Control Register Setting In Remote Update
nCONFIG reset All bits are 0
nSTATUS error All bits are 0
CORE triggered reconfiguration Update register
CRC error All bits are 0
Wd time out All bits are 0

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