220.127.116.11. Dynamic Phase Shift
The dynamic phase shifting feature allows the output phase of individual PLL outputs to be dynamically adjusted relative to each other and the reference clock without sending serial data through the scan chain of the corresponding PLL. This feature simplifies the interface and allows you to quickly adjust tCO delays by changing output clock phase shift in real time. This is achieved by incrementing or decrementing the VCO phase-tap selection to a given C counter or to the M counter. The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active during this phase reconfiguration process.
|phasecounterselect[2..0]||Counter select. Three bits decoded to select either the M or one of the C counters for phase adjustment. One address map to select all C counters. This signal is registered in the PLL on the rising edge of scanclk.||Logic array or I/O pins||PLL reconfiguration circuit|
|phaseupdown||Selects dynamic phase shift direction; 1= UP, 0 = DOWN. Signal is registered in the PLL on the rising edge of scanclk.||Logic array or I/O pins||PLL reconfiguration circuit|
|phasestep||Logic high enables dynamic phase shifting.||Logic array or I/O pins||PLL reconfiguration circuit|
|scanclk||Free running clock from core used in combination with phasestep to enable or disable dynamic phase shifting. Shared with scanclk for dynamic reconfiguration.||GCLK or I/O pins||PLL reconfiguration circuit|
|phasedone||When asserted, it indicates to core logic that the phase adjustment is complete and PLL is ready to act on a possible second adjustment pulse. Asserts based on internal PLL timing. De-asserts on the rising edge of scanclk.||PLL reconfiguration circuit||Logic array or I/O pins|
|PLL Counter Selection||PHASECOUNTERSELECT|
|All output counters||0||0||0|
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