Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.6.5. Programmable Output Slew Rate Control

You have the option of three settings for programmable slew rate control—0, 1, and 2 with 2 as the default setting. Setting 0 is the slow slew rate and 2 is the fast slew rate.
  • Fast slew rate—provides high-speed transitions for high-performance systems.
  • Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
Table 33.  Programmable Output Slew Rate Control for Intel® Cyclone® 10 LP DevicesThis table lists the I/O standards and current strength settings that support programmable output slew rate control. For I/O standards and current strength settings that do not support programmable slew rate control, the default slew rate setting is 2 (fast slew rate).
I/O Standard

IOH / IOL Current Strength Supporting Slew Rate Control

3.0 V LVTTL/3.0 V LVCMOS 16, 12, 8
2.5 V LVTTL/2.5 V LVCMOS 16, 12, 8
1.8 V LVTTL/1.8 V LVCMOS 16, 12, 10, 8
1.5 V LVCMOS 16, 12, 10, 8
1.2 V LVCMOS 12, 10, 8
SSTL-2 Class I 12, 8
SSTL-2 Class II 16
SSTL-18 Class I 12, 10, 8
SSTL-18 Class II 16, 12
1.8 V HSTL Class I 12, 10, 8
1.8 V HSTL Class II 16
1.5 V HSTL Class I 12, 10, 8
1.5 V HSTL Class II 16
1.2 V HSTL Class I 12, 10, 8
1.2 V HSTL Class II 14
Differential SSTL-2 Class I 12, 8
Differential SSTL-2 Class II 16
Differential SSTL-18 12, 10, 8
Differential 1.8 V HSTL 12, 10, 8
Differential 1.5 V HSTL 12, 10, 8
Differential 1.2 V HSTL 12, 10, 8
BLVDS 16, 12, 8

You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew rate control. The slew rate control affects both the rising and falling edges.

Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.

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