Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.6. Post-Scale Counter Cascading

The Intel® Cyclone® 10 LP PLLs support post-scale counter cascading to create counters larger than 512. This is implemented by feeding the output of one C counter into the input of the next C counter.

Figure 48. Counter-to-Counter Cascading

When cascading counters to implement a larger division of the high-frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings.

For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.

Post-scale counter cascading is automatically set by the Intel® Quartus® Prime software in the configuration file. Post-scale counter cascading cannot be performed using PLL reconfiguration.

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