Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

7.3.1. Error Detection Block

Figure 109. Error Detection Block DiagramThe figure shows the error detection block diagram with the two related 32-bit registers—the signature register and the storage register.

The error detection circuitry has two sets of 32-bit registers that store the computed CRC signature and the pre-calculated CRC value. A non-zero value on the signature register causes CRC_ERROR to go high.

Table 52.  Error Detection Registers for Intel® Cyclone® 10 LP Devices
Register Description
32-bit signature register This register contains the CRC signature. The signature register contains the result of the user mode calculated CRC value compared against the pre-calculated CRC value. If no errors are detected, the signature register is all zeroes. A non-zero signature register indicates an error in the configuration CRAM contents. The CRC_ERROR signal is derived from the contents of this register.
32-bit storage register This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration stage. The signature is then loaded into the 32-bit Compute and Compare CRC block during user mode to calculate the CRC error. This register forms a 32-bit scan chain during execution of the CHANGE_EDREG JTAG instruction. The CHANGE_EDREG JTAG instruction can change the content of the storage register. Therefore, the functionality of the error detection CRC circuitry is checked in-system by executing the instruction to inject an error during the operation. The operation of the device is not halted when issuing the CHANGE_EDREG JTAG instruction.

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