Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

5.9.5. Guideline: LVTTL or LVCMOS Inputs in Intel® Cyclone® 10 LP Devices

If you are designing LVTTL/LVCMOS inputs with Intel® Cyclone® 10 LP devices, follow these guidelines:

  • All pins accept input voltage (VI) up to a maximum limit (3.6 V) stated in the recommended operating conditions in the device datasheet.
  • Whenever the input level is higher than the bank's VCCIO, expect higher leakage current.
  • The LVTTL or LVCMOS I/O standard input pins can only conform to the VIH and VIL levels according to the bank's voltage level.

If you use an Intel® Cyclone® 10 LP device as a receiver in a 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS systems, you must manage the overshoot or undershoot to stay within the absolute maximum ratings and the recommended operating conditions. Refer to the device datasheet.