Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents LVDS I/O Standard in Intel® Cyclone® 10 LP Devices

The LVDS I/O standard is a high-speed, low-voltage swing, low power, and GPIO interface standard.
Intel® Cyclone® 10 LP devices meet the ANSI/TIA/EIA-644 standard with the following exceptions:
  • The maximum differential output voltage (VOD) is increased to 600 mV. The maximum VOD for ANSI specification is 450 mV.
  • The input voltage range is reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V, or 0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644 specification supports an input voltage range of 0 V to 2.4 V.

The Intel® Cyclone® 10 LP left and right I/O banks (row I/Os) support true LVDS transmitters. The top and bottom I/O banks support emulated LVDS transmitters with external resistors.

For the LVDS receiver, you require an external 100 Ω termination resistor between the two signals at the input buffer.

Figure 72. LVDS Interface with True Output Buffer on the Right Side I/O BanksThis figure shows a point-to-point LVDS interface using the true LVDS output and input buffers.

Figure 73. LVDS Interface with External Resistor Network on the Top and Bottom I/O BanksThis figure shows a point-to-point LVDS interface using two single-ended output buffers and external resistors. In the figure, RS is 120 Ω while RP is 170 Ω.