Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
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6.1.1.1. Active Serial Single-Device Configuration

For single-device AS configurations, connect the Intel® Cyclone® 10 LP device to a serial configuration device.

Figure 83. Active Serial Single Device Configuration

The Intel® Cyclone® 10 LP device uses the DCLK and DATA[1] pins to send operation commands and read address signals to the serial configuration device. The configuration device provides data on its DATA pin, which connects to the DATA[0] input of the Intel® Cyclone® 10 LP device. All AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal pull-up resistors that are always active. After configuration, these pins are set as input tri-stated and driven high by the weak internal pull-up resistors.

Intel® Cyclone® 10 LP generate the serial clock, DCLK, that provides timing to the serial interface. In the AS configuration scheme, Intel® Cyclone® 10 LP devices drive control signals on the falling edge of DCLK and latch the configuration data on the following falling edge of this clock pin.

The DCLK generated by the Intel® Cyclone® 10 LP device controls the entire configuration cycle and provides timing for the serial interface. Intel® Cyclone® 10 LP device uses a 40-MHz internal oscillator to generate the DCLK. There are some variations in the internal oscillator frequency because of the processes, voltage, and temperature (PVT) conditions in the Intel® Cyclone® 10 LP devices.