Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.2.6. Packed Mode Support

You can implement two single-port memory blocks in a single block under the following conditions:

  • Each of the two independent block sizes is less than or equal to half of the M9K block size. The maximum data width for each independent block is 18 bits wide.
  • Each of the single-port memory blocks is configured in single-clock mode.

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