Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

PLL Specifications

PLL specifications are for Intel® Cyclone® 10 LP devices operating in the commercial junction temperature range (0°C to 85°C), the industrial junction temperature range (–40°C to 100°C), the extended industrial junction temperature range (–40°C to 125°C), and the automotive junction temperature range (–40°C to 125°C).
Table 21.  PLL Specifications for Intel® Cyclone® 10 LP Devices

This table is applicable for general purpose PLLs and multipurpose PLLs.

You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.

Symbol Parameter Min Typ Max Unit
fIN 34 Input clock frequency (–C6, –C8, –I7, and –A7 speed grades) 5 — 472.5 MHz
Input clock frequency (–I8 speed grade) 5 — 362 MHz
fINPFD PFD input frequency 5 — 325 MHz
fVCO 35 PLL internal VCO operating range 600 — 1300 MHz
fINDUTY Input clock duty cycle 40 — 60 %
tINJITTER_CCJ 36 Input clock cycle-to-cycle jitter
FREF ≥ 100 MHz — — 0.15 UI
FREF < 100 MHz — — ±750 ps
fOUT_EXT (external clock output) 34 PLL output frequency — — 472.5 MHz
fOUT (to global clock) PLL output frequency (–C6 speed grade) — — 472.5 MHz
PLL output frequency (–I7, –A7 speed grades) — — 450 MHz
PLL output frequency (–C8 speed grade) — — 402.5 MHz
PLL output frequency (–I8 speed grade) — — 362 MHz
tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 %
tLOCK Time required to lock from end of device configuration — — 1 ms
tDLOCK Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) — — 1 ms
tOUTJITTER_PERIOD_DEDCLK 37 Dedicated clock output period jitter 
FOUT ≥ 100 MHz — — 300 ps
FOUT < 100 MHz — — 30 mUI
tOUTJITTER_CCJ_DEDCLK 37 Dedicated clock output cycle-to-cycle jitter 
FOUT ≥ 100 MHz — — 300 ps
FOUT < 100 MHz — — 30 mUI
tOUTJITTER_PERIOD_IO 37 Regular I/O period jitter
FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tOUTJITTER_CCJ_IO 37 Regular I/O cycle-to-cycle jitter
FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps
tARESET Minimum pulse width on areset signal. 10 — — ns
tCONFIGPLL Time required to reconfigure scan chains for PLLs — 3.5 38 — SCANCLK cycles
fSCANCLK scanclk frequency — — 100 MHz
tCASC_OUTJITTER_PERIOD_DEDCLK 39 40 Period jitter for dedicated clock output in cascaded PLLs (FOUT ≥ 100 MHz) — — 425 ps
Period jitter for dedicated clock output in cascaded PLLs (FOUT ≥ 100 MHz) — — 42.5 mUI
34 This parameter is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
35 The VCO frequency reported by the Intel® Quartus® Prime software in the PLL Summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
36 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less than 200 ps.
37 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
38 With 100-MHz scanclk frequency.
39 The cascaded PLLs specification is applicable only with the following conditions:
  • Upstream PLL—0.59 MHz ≥ Upstream PLL bandwidth < 1 MHz
  • Downstream PLL—Downstream PLL bandwidth > 2 MHz
40 PLL cascading is not supported for transceiver applications.
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