Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

LVDS Receiver Timing Specifications

Table 29.  LVDS Receiver Timing Specifications for Intel® Cyclone® 10 LP DevicesLVDS receiver is supported at all I/O Banks.
Symbol Modes C6 I7 C8, A7 I8 Unit
Min Max Min Max Min Max Min Max
fHSCLK (input clock frequency) ×10 10 437.5 10 370 10 320 10 320 MHz
×8 10 437.5 10 370 10 320 10 320 MHz
×7 10 437.5 10 370 10 320 10 320 MHz
×4 10 437.5 10 370 10 320 10 320 MHz
×2 10 437.5 10 370 10 320 10 320 MHz
×1 10 437.5 10 402.5 10 402.5 10 362 MHz
HSIODR ×10 100 875 100 740 100 640 100 640 Mbps
×8 80 875 80 740 80 640 80 640 Mbps
×7 70 875 70 740 70 640 70 640 Mbps
×4 40 875 40 740 40 640 40 640 Mbps
×2 20 875 20 740 20 640 20 640 Mbps
×1 10 437.5 10 402.5 10 402.5 10 362 Mbps
SW — — 400 — 400 — 400 — 550 ps
Input jitter tolerance — — 500 — 500 — 550 — 600 ps
tLOCK 46 — — 1 — 1 — 1 — 1 ms
46 tLOCK is the time required for the PLL to lock from the end-of-device configuration.
Level Two Title