Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
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LVDS Receiver Timing Specifications

Table 29.  LVDS Receiver Timing Specifications for Intel® Cyclone® 10 LP DevicesLVDS receiver is supported at all I/O Banks.
Symbol Modes C6 I7 C8, A7 I8 Unit
Min Max Min Max Min Max Min Max
fHSCLK (input clock frequency) ×10 10 437.5 10 370 10 320 10 320 MHz
×8 10 437.5 10 370 10 320 10 320 MHz
×7 10 437.5 10 370 10 320 10 320 MHz
×4 10 437.5 10 370 10 320 10 320 MHz
×2 10 437.5 10 370 10 320 10 320 MHz
×1 10 437.5 10 402.5 10 402.5 10 362 MHz
HSIODR ×10 100 875 100 740 100 640 100 640 Mbps
×8 80 875 80 740 80 640 80 640 Mbps
×7 70 875 70 740 70 640 70 640 Mbps
×4 40 875 40 740 40 640 40 640 Mbps
×2 20 875 20 740 20 640 20 640 Mbps
×1 10 437.5 10 402.5 10 402.5 10 362 Mbps
SW 400 400 400 550 ps
Input jitter tolerance 500 500 550 600 ps
tLOCK 46 1 1 1 1 ms
46 tLOCK is the time required for the PLL to lock from the end-of-device configuration.