Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
Public
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Glossary

Terms

  • Receiver input skew margin (RSKM)—High-speed I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2.
  • SW (Sampling Window)—High-speed I/O block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window.

Clock Pins and Blocks

  • fHSCLK—High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
  • GCLK—Input pin directly to Global Clock network.
  • GCLK PLL—Input pin to Global Clock network through the PLL.
  • HSIODR—High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
  • PLL Block—The following figure highlights the PLL specification parameters
  • RL—Receiver differential input discrete resistor (external to Intel® Cyclone® 10 LP devices).

Example Waveforms

Input Waveforms for the SSTL Differential I/O Standard

JTAG Waveform

Receiver Waveform for LVDS and LVPECL Differential Standards

Single-Ended Voltage-Referenced I/O Standard

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.

Transmitter Output Waveform for the LVDS, Mini-LVDS, PPDS and RSDS Differential I/O Standards:

Delay Definitions

  • tC—High-speed receiver and transmitter input and output clock period.
  • Channel-to-channel-skew (TCCS)—High-speed I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement.
  • tcin—Delay from the clock pad to the I/O input register.
  • tCO—Delay from the clock pad to the I/O output.
  • tcout—Delay from the clock pad to the I/O output register.
  • tDUTY—High-speed I/O block: Duty cycle on high-speed transmitter output clock.
  • tFALL—Signal high-to-low transition time (80–20%).
  • tH—Input register hold time.
  • Timing Unit Interval (TUI)—High-speed I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
  • tINJITTER—Period jitter on the PLL clock input.
  • tOUTJITTER_DEDCLK—Period jitter on the dedicated clock output driven by a PLL.
  • tOUTJITTER_IO—Period jitter on the general purpose I/O driven by a PLL.
  • tpllcin—Delay from the PLL inclk pad to the I/O input register.
  • tpllcout—Delay from the PLL inclk pad to the I/O output register.
  • tRISE—Signal low-to-high transition time (20–80%).
  • tSU—Input register setup time.

Voltage Definitions

  • VCM(DC)—DC common mode input voltage.
  • VDIF(AC)—AC differential input voltage: The minimum AC input differential voltage required for switching.
  • VDIF(DC)—DC differential input voltage: The minimum DC input differential voltage required for switching.
  • VICM—Input common mode voltage: The common mode of the differential signal at the receiver.
  • VID—Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
  • VIH—Voltage input high: The minimum positive voltage applied to the input that is accepted by the device as a logic high.
  • VIH(AC)—High-level AC input voltage.
  • VIH(DC)—High-level DC input voltage.
  • VIL—Voltage input low: The maximum positive voltage applied to the input that is accepted by the device as a logic low.
  • VIL (AC)—Low-level AC input voltage.
  • VIL (DC)—Low-level DC input voltage.
  • VIN—DC input voltage.
  • VOCM—Output common mode voltage: The common mode of the differential signal at the transmitter.
  • VOD—Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
  • VOH—Voltage output high: The maximum positive voltage from an output that the device considers is accepted as the minimum positive high level.
  • VOL—Voltage output low: The maximum positive voltage from an output that the device considers is accepted as the maximum positive low level.
  • VOS—Output offset voltage: VOS = (VOH + VOL) / 2.
  • VOX (AC)—AC differential output cross point voltage: the voltage at which the differential output signals must cross.
  • VREF—Reference voltage for the SSTL and HSTL I/O standards.
  • VREF (AC)—AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC).
  • VREF (DC)—DC input reference voltage for the SSTL and HSTL I/O standards.
  • VSWING (AC)—AC differential input voltage: AC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms.
  • VSWING (DC)—DC differential input voltage: DC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms.
  • VTT—Termination voltage for the SSTL and HSTL I/O standards.
  • VX (AC)—AC differential input cross point voltage: The voltage at which the differential input signals must cross.