Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

IOE Programmable Delay

The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Intel® Quartus® Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings).

The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Intel® Quartus® Prime software.

Table 32.  IOE Programmable Delay on Column Pins for Intel® Cyclone® 10 LP 1.0 V Core Voltage Devices
Parameter Paths Affected Number of Setting Min Offset Max Offset Unit
Fast Corner Slow Corner
I8 I8
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.924 3.411 ns
Input delay from pin to input register Pad to I/O input register 8 0 1.875 3.367 ns
Delay from output register to output pin I/O output register to pad 2 0 0.631 1.124 ns
Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.931 1.684 ns
Table 33.  IOE Programmable Delay on Row Pins for Intel® Cyclone® 10 LP 1.0 V Core Voltage Devices
Parameter Paths Affected Number of Setting Min Offset Max Offset Unit
Fast Corner Slow Corner
I8 I8
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.921 3.412 ns
Input delay from pin to input register Pad to I/O input register 8 0 1.919 3.441 ns
Delay from output register to output pin I/O output register to pad 2 0 0.623 1.168 ns
Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.919 1.656 ns
Table 34.  IOE Programmable Delay on Column Pins for Intel® Cyclone® 10 LP 1.2 V Core Voltage Devices
Parameter Paths Affected Number of Setting Min Offset Max Offset Unit
Fast Corner Slow Corner
C6 I7 A7 C6 C8 I7 A7
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.314 1.211 1.211 2.177 2.433 2.388 2.508 ns
Input delay from pin to input register Pad to I/O input register 8 0 1.307 1.203 1.203 2.19 2.540 2.430 2.545 ns
Delay from output register to output pin I/O output register to pad 2 0 0.437 0.402 0.402 0.747 0.880 0.834 0.873 ns
Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.693 0.665 0.665 1.200 1.532 1.393 1.441 ns
Table 35.  IOE Programmable Delay on Row Pins for Intel® Cyclone® 10 LP 1.2 V Core Voltage Devices
Parameter Paths Affected Number of Setting Min Offset Max Offset Unit
Fast Corner Slow Corner
C6 I7 A7 C6 C8 I7 A7
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.314 1.209 1.209 2.201 2.510 2.429 2.548 ns
Input delay from pin to input register Pad to I/O input register 8 0 1.312 1.207 1.207 2.202 2.558 2.447 2.557 ns
Delay from output register to output pin I/O output register to pad 2 0 0.458 0.419 0.419 0.783 0.924 0.875 0.915 ns
Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.686 0.657 0.657 1.185 1.506 1.376 1.422 ns
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