Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

Memory Block Specifications

Table 23.  M9K Memory Block Performance Specifications for Intel® Cyclone® 10 LP Devices
Memory Mode Resources Used Performance Unit
LEs M9K Memory C6 I7, A7 C8 I8
M9K Block FIFO 256 × 36 47 1 315 274 238 200 MHz
Single-port 256 × 36 0 1 315 274 238 200 MHz
Simple dual-port 256 × 36 CLK 0 1 315 274 238 200 MHz
True dual port 512 × 18 single CLK 0 1 315 274 238 200 MHz
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