Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
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JTAG Timing Parameters

Table 36.  JTAG Timing Parameters for Intel® Cyclone® 10 LP Devices
Symbol Parameter Min Max Unit
tJCP TCK clock period 40 ns
tJCH TCK clock high time 19 ns
tJCL TCK clock low time 19 ns
tJPSU_TDI JTAG port setup time for TDI 1 ns
tJPSU_TMS JTAG port setup time for TMS 3 ns
tJPH JTAG port hold time 10 ns
tJPCO JTAG port clock to output 47 15 ns
tJPZX JTAG port high impedance to valid output 47 15 ns
tJPXZ JTAG port valid output to high impedance 47 15 ns
tJSSU Capture register setup time 5 ns
tJSH Capture register hold time 10 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
47 The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.