Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
Public
Document Table of Contents
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I/O Timing

I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script.

The Intel® Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.