Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

Recommended Operating Conditions

This section describes the functional operation limits for AC and DC parameters for Intel® Cyclone® 10 LP devices.
Table 3.  Recommended Operating Conditions for Intel® Cyclone® 10 LP Devices

This table lists the steady-state voltage and current values expected from Intel® Cyclone® 10 LP devices. All supplies must be strictly monotonic without plateaus.

VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.

Symbol Parameter Condition Min Typ Max Unit
VCCINT 1 Supply voltage for internal logic 1.2-V operation 1.15 1.2 1.25 V
1.0-V operation 0.97 1.0 1.03 V
VCCIO 1 2 Supply voltage for output buffers 3.3-V operation 3.135 3.3 3.465 V
3.0-V operation 2.85 3 3.15 V
2.5-V operation 2.375 2.5 2.625 V
1.8-V operation 1.71 1.8 1.89 V
1.5-V operation 1.425 1.5 1.575 V
1.2-V operation 1.14 1.2 1.26 V
VCCA 1 Supply (analog) voltage for PLL regulator — 2.375 2.5 2.625 V
VCCD_PLL 1 Supply (digital) voltage for PLL 1.2-V operation 1.15 1.2 1.25 V
1.0-V operation 0.97 1.0 1.03 V
VI Input voltage — –0.5 — 3.6 V
VO Output voltage — 0 — VCCIO V
TJ Operating junction temperature For commercial use 0 — 85 °C
For industrial use –40 — 100 °C
For extended temperature 3 –40 — 125 °C
For automotive use –40 — 125 °C
tRAMP Power supply ramp time Standard power-on reset (POR) 4 50 µs — 50 ms —
Fast POR 5 50 µs — 3 ms —
IDiode Magnitude of DC current across PCI* -clamp diode when enable — — — 10 mA
Related Information
1 VCC must rise monotonically.
2 VCCIO powers all input buffers.
3 Refer to the Extended Temperature Device Support page for more details about the support.
4 The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms.
5 The POR time for fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.
Level Two Title