Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
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Emulated LVDS Transmitter Timing Specifications

Table 28.  Emulated LVDS Transmitter Timing Specifications for Intel® Cyclone® 10 LP DevicesEmulated LVDS transmitter is supported at the output pin of all I/O Banks.
Symbol Modes C6 I7 C8, A7 I8 Unit
Min Max Min Max Min Max Min Max
fHSCLK (input clock frequency) ×10 5 320 5 320 5 275 5 275 MHz
×8 5 320 5 320 5 275 5 275 MHz
×7 5 320 5 320 5 275 5 275 MHz
×4 5 320 5 320 5 275 5 275 MHz
×2 5 320 5 320 5 275 5 275 MHz
×1 5 402.5 5 402.5 5 402.5 5 362 MHz
HSIODR ×10 100 640 100 640 100 550 100 550 Mbps
×8 80 640 80 640 80 550 80 550 Mbps
×7 70 640 70 640 70 550 70 550 Mbps
×4 40 640 40 640 40 550 40 550 Mbps
×2 20 640 20 640 20 550 20 550 Mbps
×1 10 402.5 10 402.5 10 402.5 10 362 Mbps
tDUTY 45 55 45 55 45 55 45 55 %
TCCS 200 200 200 200 ps
Output jitter
(peak to peak) 500 500 550 600 ps
tLOCK 45 1 1 1 1 ms
45 tLOCK is the time required for the PLL to lock from the end-of-device configuration.