Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

Differential I/O Standard Specifications

Table 19.  Differential I/O Standard Specifications for Intel® Cyclone® 10 LP Devices
I/O Standard VCCIO (V) VID (mV) VIcM (V)  29 VOD (mV)   30 VOS (V)  30
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
LVPECL (Row I/Os) 31 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.80 — — — — — —
0.55 ≤  500 Mbps   DMAX ≤   700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
LVPECL (Column I/Os) 31 2.375 2.5 2.625 100 — 0.05 DMAX≤      500 Mbps 1.80 — — — — — —
0.55 500 Mbps  ≤   DMAX ≤ 700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
LVDS (Row I/Os) 2.375 2.5 2.625 100 — 0.05 DMAX≤    500 Mbps 1.80 247 — 600 1.125 1.25 1.375
0.55 500 Mbps  ≤   DMAX ≤    700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
LVDS (Column I/Os) 2.375 2.5 2.625 100 — 0.05 DMAX ≤     500 Mbps 1.80 247 — 600 1.125 1.25 1.375
0.55 500 Mbps  ≤   DMAX ≤    700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
BLVDS (Row I/Os) 32 2.375 2.5 2.625 100 — — — — — — — — — —
BLVDS (Column I/Os) 32 2.375 2.5 2.625 100 — — — — — — — — — —
mini-LVDS (Row I/Os) 33 2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4
mini-LVDS (Column I/Os) 33 2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4
RSDS (Row I/Os) 33 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5
RSDS (Column I/Os) 33 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5
PPDS (Row I/Os) 33 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4
PPDS (Column I/Os) 33 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4
29 VIN range: 0 V ≤ VIN ≤ 1.85 V.
30 RL range: 90 ≤ RL ≤ 110 Ω.
31 The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.
32 There are no fixed VIN, VOD , and VOS specifications for BLVDS. They depend on the system topology.
33 The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins.
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