Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
Public
Document Table of Contents

Mini-LVDS Transmitter Timing Specifications

Table 26.  Mini-LVDS Transmitter Timing Specifications for Intel® Cyclone® 10 LP Devices

Applicable for true and emulated mini-LVDS transmitter.

True mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at the output pin of all I/O banks.

Symbol Modes C6 I7 C8, A7 I8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (input clock frequency) ×10 5 200 5 155.5 5 155.5 5 155.5 MHz
×8 5 200 5 155.5 5 155.5 5 155.5 MHz
×7 5 200 5 155.5 5 155.5 5 155.5 MHz
×4 5 200 5 155.5 5 155.5 5 155.5 MHz
×2 5 200 5 155.5 5 155.5 5 155.5 MHz
×1 5 400 5 311 5 311 5 311 MHz
Device operation in Mbps ×10 100 400 100 311 100 311 100 311 Mbps
×8 80 400 80 311 80 311 80 311 Mbps
×7 70 400 70 311 70 311 70 311 Mbps
×4 40 400 40 311 40 311 40 311 Mbps
×2 20 400 20 311 20 311 20 311 Mbps
×1 10 400 10 311 10 311 10 311 Mbps
tDUTY 45 55 45 55 45 55 45 55 %
TCCS 200 200 200 200 ps
Output jitter
(peak to peak) 500 500 550 600 ps
tRISE 20 – 80%,
CLOAD = 5 pF 500 500 500 500 ps
tFALL 20 – 80%,
CLOAD = 5 pF 500 500 500 500 ps
tLOCK 43 1 1 1 1 ms
43 tLOCK is the time required for the PLL to lock from the end-of-device configuration.