Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
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Emulated RSDS_E_1R Transmitter Timing Specifications

Table 25.  Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® Cyclone® 10 LP DevicesEmulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks.
Symbol Modes C6 I7 C8, A7 I8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (input clock frequency) ×10 5 85 5 85 5 85 5 85 MHz
×8 5 85 5 85 5 85 5 85 MHz
×7 5 85 5 85 5 85 5 85 MHz
×4 5 85 5 85 5 85 5 85 MHz
×2 5 85 5 85 5 85 5 85 MHz
×1 5 170 5 170 5 170 5 170 MHz
Device operation in Mbps ×10 100 170 100 170 100 170 100 170 Mbps
×8 80 170 80 170 80 170 80 170 Mbps
×7 70 170 70 170 70 170 70 170 Mbps
×4 40 170 40 170 40 170 40 170 Mbps
×2 20 170 20 170 20 170 20 170 Mbps
×1 10 170 10 170 10 170 10 170 Mbps
tDUTY 45 55 45 55 45 55 45 55 %
TCCS 200 200 200 200 ps
Output jitter
(peak to peak) 500 500 550 600 ps
tRISE 20 – 80%,

CLOAD = 5 pF

500 500 500 500 ps
tFALL 20 – 80%,

CLOAD = 5 pF

500 500 500 500 ps
tLOCK 42 1 1 1 1 ms
42 tLOCK is the time required for the PLL to lock from the end-of-device configuration.