Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
ID
813775
Date
4/07/2025
Public
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Altera Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
1. Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
Configuration via Protocol (CvP) is a configuration scheme supported in Arria® V, Cyclone® V, Stratix® V, Arria® 10, Stratix® 10, Cyclone® 10 GX, and Agilex™ FPGAs. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Altera FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only.
This document describes the CvP configuration scheme for Agilex™ 5 FPGAs.
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