Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide

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UG-20045 | 2021.02.19

Version Information

Updated for:
Intel® Quartus® Prime Design Suite 19.3

1. Overview

Configuration via Protocol (CvP) is a configuration scheme supported in Arria^® V, Cyclone^® V, Stratix^® V, Intel^® Arria^® 10, Intel^® Stratix^® 10, and Intel^® Cyclone^® 10 GX device families. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Intel^® FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only. This document describes the CvP configuration scheme for Intel^® Stratix^® 10 device family. The CvP configuration scheme targets core fabric configuration through PCIe* link, which means it only supports FPGA Configuration First Mode even you use Intel^® Stratix^® 10 SoC devices.

1.1. Benefits of Using CvP

The CvP configuration scheme has the following advantages:

Reduces system costs by reducing the size of the local flash device that stores the configuration data. The smallest EPCQ-L device is large enough for all Intel^® Stratix^® 10 periphery images.
Allows update of the FPGA without reprogramming the flash.
Enables dynamic core updates without requiring a system power down. CvP allows you to update the FPGA core fabric through the PCIe* link without a host reboot or FPGA full chip reinitialization.
Provides a simpler software model for configuration. A smart host can use the PCIe* protocol and the application topology to initialize and update the FPGA core fabric.
Allows quick update of your design for changing application loads.

1.2. CvP System

A CvP system typically consists of an FPGA, a PCIe* host, and a configuration device.

Figure 1. CvP Block Diagram

The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme.
CvP and other applications use the PCIe* Hard IP block (bottom left).
Note: For information about the location of the PCIe* Hard IP blocks, refer to Table: PCIe Hard IP channel mapping across all tiles in Channel Availability section of the Intel Stratix 10 H-Tile and L-Tile Avalon Memory Mapped Hard IP for PCI Express* User Guide.
- Many Intel^® Stratix^® 10 FPGAs include more than one Hard IP block for PCI Express* . The CvP configuration scheme can only utilize the bottom left PCIe* Hard IP block on each device. You must configure this as an Endpoint.
PCIe* Hard IP tile (non-bottom left tile) can only be used for PCIe* applications and cannot be used for CvP.

Note: To avoid configuration failure, you must provide a free running and stable reference clock source to PCIe* IP core before you start the configuration.

Note: For PCIe design including Configuration via Protocol (CvP), Intel recommends you to use Micron QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM will read the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM will read the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Intel recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enter link training state before PERST# deasserted.

1.3. CvP Modes

The CvP configuration scheme supports the following modes:

CvP Initialization mode
CvP Update mode

CvP Initialization Mode

This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs through PCIe* link.

Benefits of using CvP Initialization mode include:

Satisfying the PCIe* wake-up time requirement
Saving cost by storing the core image in the host memory

CvP Update Mode

In the CvP update mode, you reconfigure the entire device except the CvP PCIe* core after the device enters the user mode through full chip configuration or CvP initialization. The subsequent core image updates use the PCIe* link (the periphery must not change during CvP update).

The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.

Choose this mode if you want to update the core image for any of the following reasons:

To change core algorithms logic blocks
To perform standard updates as part of a release process
To customize core processing for different components that are part of a complex system

Note: The CvP update mode is available after the FPGA enters user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.

Table 1. CvP Support for Intel^® Stratix^® 10 Device Family
Supported Tile	PCIe* Version	Supported CvP Modes
H- and L-tile	Gen 1 / Gen 2 / Gen 3	CvP Initialization, CvP Update
P-tile	Gen 1 / Gen 2 / Gen 3 / Gen 4 Note: You can only select Gen 3 and above in the PCIe* Hard IP, but the host can down-train the link to Gen 1 and Gen 2 if necessary. Note: P-tile Gen 3x8 and Gen 4x8 cannot support CvP.	CvP Initialization, CvP Update

1.3.1. CvP Limitations and Restrictions

The Intel^® Stratix^® 10 CvP implementation has the following limitations and restrictions in the current version of the Intel^® Quartus^® Prime software:

Only MemWR transactions can be used to write fabric configuration data to the CvP data register. ConfigWR transactions are not supported.
When you poll the CVP_CREDIT bits from the CvP credit register, you must write the next 4KB of fabric configuration data to the CvP data register within 50 ms of receiving an additional credit. Failure to send the data results in configuration failure.
The CvP response time is variable and depends on different conditions. The typical delay time is 5 sec and it is safe to wait till 1 min. So the driver should poll status in credit register to decide on driver timeout.
In CvP initialization and update mode, when FPGA fabric is not programmed, the PCIe* features that uses FPGA fabric are not accessible.
To generate the update image in the CvP update mode, you must use the same version of the Intel^® Quartus^® Prime software that you use to generate the base image.

1.3.1.1. CvP Error Recovery

This section describes expected behavior during different error situations.

Table 2. Intel^® Stratix^® 10 CvP Error Events and Suggested Recovery Methods
Error Events	Suggested Recovery Method
A bitstream is corrupted within the first 168KB of data.	The `CVP_CONFIG_ERROR` bit in the CvP status register goes high. Go through the Teardown sequence prior to sending another bitstream.
A bitstream is corrupted after the first 168KB of data.	The `CVP_CONFIG_ERROR` bit in the CvP status register goes high. To recover the system, you must power-cycle the targeted Intel^® Stratix^® 10 device.
PCIe* bus error during CvP	System is unrecoverable and you must power-cycle the system.
PCIe* bus error results in PERST assert.	System is unrecoverable and you must power-cycle the system.
CvP operation requests to abort	Unsupported. Aborting configuration after requesting CvP operation is not supported. Intel^® recommends to power-cycle the system.
A bitstream is provided from a Intel^® Quartus^® Prime version other than the one used to generate configuration firmware currently running in the device.	The `CVP_CONFIG_ERROR` bit in the CvP status register goes high. Go through the Teardown sequence prior to sending another bitstream. Mixing bitstreams from different Quartus versions is not supported.

2. CvP Description

2.1. Configuration Images

In CvP, you split your bitstream into two images: periphery image and core image.

You use the Intel^® Quartus^® Prime Pro Edition software to generate the images:

Periphery image (*.periph.jic) — contains only CvP PCIe core. The entire periphery image is static and cannot be reconfigured.
Core image (*.core.rbf) — contains the entire device except the CvP PCIe core.

2.2. CvP Modes

2.2.1. CvP Initialization Mode

In this mode, an external configuration device stores the periphery image and it loads into the FPGA through the Active Serial x4 (Fast mode) configuration scheme. The host memory stores the core image and it loads into the FPGA through the PCIe* link.

After the periphery image configuration is complete, the CONF_DONE signal goes high and the FPGA starts PCIe* link training. When PCIe* link training is complete, the PCIe* link transitions to L0 state and then allows the host to complete PCIe* enumeration of the link. The PCIe* host then initiates the core image configuration through the PCIe* link. The PCIe* REFCLK needs to be running prior to sending the periphery image.

After the core image configuration is complete, the CvP_CONFDONE pin (if enabled) goes high, indicating the FPGA is fully configured.

After the FPGA is fully configured, the FPGA enters user mode. If the INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is complete and the FPGA enters the user mode.

In user mode, the PCIe* links are available for normal PCIe* applications.

2.2.2. CvP Update Mode

CvP update mode is a reconfiguration scheme that allows a host device to deliver an updated bitstream to a target FPGA device after the device enters user mode. In this mode, the FPGA device initializes by loading the full configuration image from any supported configuration scheme to the FPGA or after CvP initialization.

You can perform CvP update on a device that you originally configure using CvP initialization or any other configuration scheme. CvP initialization is not a prerequisite for performing CvP update.

In user mode, the PCIe* links are available for normal PCIe* applications. You can use the CvP PCIe* link to perform an FPGA core image update. To perform the FPGA core image update, you can create one or more FPGA core images in the Intel^® Quartus^® Prime Pro Edition software that have identical connections to the periphery image.

Figure 2. Periphery and Core Image Storage Arrangement for CvP Core Image UpdateThe periphery image remains the same for different core image updates. If you change the periphery image, you must reprogram the local configuration device with the new periphery image.

2.3. Compression Features

Data Compression

The Intel^® Quartus^® Prime Pro Edition software compresses all Intel^® Stratix^® 10 bitstreams to reduce the storage requirement and increase bitstream processing speed. The periphery and core images are both compressed.

2.4. Pin Description

The following table lists the CvP pin descriptions and connection guidelines:

Table 3. CvP Pin Descriptions and Connection Guidelines
Pin Name	Pin Type	Pin Description	Pin Connection
`CvP_CONFDONE`	Output	The `CvP_CONFDONE` pin is driven low during configuration. When configuration via PCIe* is complete, this signal is actively driven high. During FPGA configuration in CvP initialization and update mode, you may observe this pin after the `CONF_DONE` pin goes high to determine if the FPGA is successfully configured.	If this pin is set as dedicated output, the `VCCIO_SDM` power supply must meet the input voltage specification of the receiving side. You can assign `SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15 or SDM_IO16` as `CvP_CONFDONE` in Intel^® Quartus^® Prime Pro Edition software
`INIT_DONE`	Output	The `INIT_DONE` pin goes high indicating the device has entered user mode upon completion of configuration.	Intel recommends using `SDM_IO0` pin for implementing the `INIT_DONE` function, provided that this function is enabled in the Intel^® Quartus^® Prime Pro Edition software. This pin has a weak pull-down for the correct function during power up. The `INIT_DONE` function can also be implemented using other unused SDM I/O pins (with a weak pull-down).
`CONF_DONE`	Output	For normal configuration mode, the `CONF_DONE` pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, `CONF_DONE` is driven high. In CvP initialization mode, `CONF_DONE` goes high after the periphery is configured.	Intel recommends using `SDM_IO16` pin implementing the `CONF_DONE` function, provided that this function is enabled in the Intel^® Quartus^® Prime Pro Edition software.
`nPERST[L,R][0:2]`	Input	The nPERST pin is only available when you use PCI Express* hard IP. When the PCIe* hard IP on a side (left or right) is enabled, then nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe* nPERST signal to ensure that both ends of the link start link-training at the same time. The nPERST pins on a side are available as GPIOs only when the PCIe* hard IP on that side is not enabled. When this pin is low, the transceivers are in reset. When this pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin	Connect this pin as defined in the Intel^® Quartus^® Prime Pro Edition software. For more details, refer to Intel^® Stratix^® 10 Avalon^® -MM/ST Interface for PCIe* Solutions User Guide. This pin is powered by the `VCCIO3V` supply. When you connect a 3.0-V supply to `VCCIO3V`, you must use a diode to clamp the `3.3V LVTTL` PCIe* input signal to the `VCCIO3V` power of the device. When `VCCIO3`V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from `3.3V LVTTL` to the corresponding voltage level powering the `VCCIO3V` pin. Only one `nPERST` pin is used per PCIe* hard IP. The Intel^® Stratix^® 10 device components may have all six pins listed even when the specific component might only have 1 or 2 PCIe* hard IPs: `nPERSTL0` = Bottom Left PCIe* hard IP & CvP `nPERSTL1` = Middle Left PCIe* hard IP (When available) `nPERSTL2` Top Left PCIe* hard IP (When available) `nPERSTR0` = Bottom Right PCIe* hard IP (When available) `nPERSTR1` = Middle Right PCIe* hard IP (When available) `nPERSTR2` = Top Right PCIe* hard IP (When available) Note: For maximum compatibility, always use the bottom left PCIe* Hard IP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe* link.

3. CvP Topologies

CvP supports two types of topologies that allow you to configure single or multiple FPGAs.

3.1. Single Endpoint

Use the single endpoint topology to configure a single FPGA. In this topology, the PCIe* link connects one PCIe* endpoint in the FPGA device to one PCIe* root port in the host.

Figure 3. Single Endpoint Topology

3.2. Multiple Endpoints

Use the multiple endpoints topology to configure multiple FPGAs through a PCIe* switch. This topology provides you with the flexibility to select the device to be configured or update through the PCIe* link. You can connect any number of FPGAs to the host in this topology.

The PCIe* switch controls the core image configuration through the PCIe* link to the targeted PCIe* endpoint in the FPGA. You must ensure that the root port can respond to the PCIe* switch and direct the configuration transaction to the designated endpoint based on the bus/device/function address of the endpoint specified by the PCIe* switch.

Figure 4. Multiple Endpoints Topology

4. Design Considerations

4.1. Designing CvP for an Open System

Follow these guidelines when designing an open CvP system where you do not have complete control of both ends of the PCIe* link.

4.1.1. FPGA Power Supplies Ramp Time Requirement

For an open system, you must ensure that your design adheres to the FPGA power supplies ramp-up time requirement.

The power-on reset (POR) circuitry keeps the FPGA in the reset state until the power supply outputs are in the recommended operating range. A POR event occurs from when you power up the FPGA until the power supplies reach the recommended operating range within the maximum power supply ramp time, t_RAMP . If t_RAMP is not met, the device I/O pins and programming registers remain tri-stated, during which device configuration could fail.

To meet the PCIe* link up time for CvP, the total t_RAMP must be less than 10 ms, from the first power supply ramp-up to the last power supply ramp-up. You must select ASx4 fast mode for MSEL settings to make sure the shortest POR delay.

Figure 5. Power Supplies Ramp-Up Time and POR

4.1.2. PCIe Wake-Up Time Requirement

For an open system, you must ensure that the PCIe* link meets the PCIe* wake-up time requirement as defined in the PCI Express* CARD Electromechanical Specification. The transition from power-on to the link active (L0) state for the PCIe* wake-up timing specification must be within 200 ms. The timing from FPGA power-up until the Hard IP for PCI Express* IP Core in the FPGA is ready for link training must be within 120 ms.

4.1.2.1. For CvP Initialization Mode

To meet the 120 ms wake-up time requirement for the PCIe* Hard IP in CvP initialization mode, you need to use periphery image because the configuration time for periphery image is significantly less than the full FPGA configuration time. You must use the Active Serial x4 (fast mode) configuration scheme for the periphery image configuration.

To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable¹. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP Initialization mode, the PCIe* link supports the FPGA core image configuration and subsequent PCIe* applications in user mode.

Note: For Gen 2/Gen 3 capable Endpoints, after loading the core bitstream (core.rbf), Intel recommends to verify that the link has been trained to the expected Gen 2/Gen3 rate. If the link is not operating at Gen 2/Gen3, software can trigger the Endpoint to retrain.

Figure 6. PCIe* Timing Sequence in CvP Initialization Mode

Table 4. Power-Up Sequence Timing in CvP Initialization Mode
Timing Sequence	Timing Range (ms)	Description
a	2-6.5	FPGA POR delay time (AS Fast Mode)
b	80	Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (before transceiver calibration)
c	20	Minimum calibration time before `PERST#` is deasserted
d	60	Minimum transceiver calibration window
e	80	Typical transceiver calibration window
f	100	Minimum `PERST#` signal active from the host
g	120	Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (include transceiver calibration)
h	20	Maximum `PERST#` signal inactive time from the host before the PCIe* link enters training state
i	100	Maximum time PCIe* device must enter L0 after `PERST#` is deasserted Note: 100 ms timing range is only applicable to PCIe* Gen1/Gen2. PCIe* Gen 3 does not need to meet 100 ms timing requirement.
j	10	Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range

¹ REFCLK must be stable 80 ms after the power supplies are stable in order to achieve the 145 ms link training complete time

4.1.2.2. For CvP Update Mode

Before you perform CvP update mode, the device must be in user mode.

Note: For Gen 2/Gen 3 capable Endpoints, in user mode, Intel recommends to verify that the link has been trains to the expected Gen 2/Gen 3 rate. If the link is not operating at Gen 2/Gen3, software can trigger the Endpoint to retrain.

4.2. Designing CvP for a Closed System

While designing CvP for a closed system where you control both ends of the PCIe* link, estimate the periphery configuration time for CvP Initialization mode or full FPGA configuration time for CvP update mode. You must ensure that the estimated configuration time is within the time allowed by the PCIe* host. Your driver can poll the USERMODE bit of the CvP Status Register to determine if the FPGA enters the user mode.

5. CvP Driver and Registers

5.1. CvP Driver Support

You can develop your own custom CvP driver for Linux using the sample Linux driver source code provided by Intel.

Note:

The Linux driver provided by Intel^® is not a production driver. You must adapt this driver to your design's strategy.

5.2. CvP Driver Flow

The CvP driver flow assumes that the FPGA is powered up and the SDM control block has already configured the FPGA with the periphery image, which is indicated by the CVP_EN bit in the CvP status register.

Figure 7. CvP Driver Flow

5.3. VSEC Registers for CvP

The Vendor Specific Extended Capability (VSEC) registers occupy byte offsets 0xB80 to 0xBC0 in the PCIe* Configuration Space. The PCIe* host uses these registers to communicate with the FPGA control block. The following table shows the VSEC register map. Subsequent tables provide the fields and descriptions of each register.

Table 5. VSEC Registers for CvP
Byte Offset	Register Name
0xB80	Vendor Specific Capability Header
0xB84	Vendor Specific Header
0xB88	Intel Marker
0xB8C:0xB98	Reserved
0xB9C	User Configurable Device/Board ID
0xB9E	CvP Status
0xBA0	CvP Mode Control
0xBA4	CvP Data 2²
0xBA8	CvP Data
0xBAC	CvP Programming Control
0xBB0:0xBC4	Reserved
0xBC8	CvP Credit Register

² This register is no longer functional in Intel^® Stratix^® 10 devices.

5.3.1. Vendor Specific Capability Header Register

Table 6. Vendor Specific Capability Header Register (Byte Offset: 0xB80)
Bits	Name	Reset Value	Access	Description
[15:0]	PCI Express* Extended Capability ID	0x000B	RO	PCIe* specification defined value for VSEC Capability ID.
[19:16]	Version	0x1	RO	PCIe* specification defined value for VSEC version.
[31:20]	Next Capability Offset	Variable	RO	Starting address of the next Capability Structure implemented, if any.

5.3.2. Vendor Specific Header Register

Table 7. Vendor Specific Header Register (Byte Offset: 0xB84)
Bits	Name	Reset Value	Access	Description
[15:0]	VSEC ID	0x1172	RO	A user configurable VSEC ID.
[19:16]	VSEC Revision	0	RO	A user configurable VSEC revision.
[31:20]	VSEC Length	0x05C	RO	Total length of this structure in bytes.

5.3.3. Intel Marker Register

Table 8. Intel Marker Register (Byte Offset: 0xB88)
Bits	Name	Reset Value	Access	Description
[31:0]	Intel Marker	0x41721172	RO	An additional marker.

5.3.4. User Configurable Device/Board ID Register

Table 9. User Configurable Device/Board ID Register (Byte Offset: 0xB9C)
Bits	Name	Reset Value	Access	Description
[15:0]	User Configurable Device/Board ID	0x00	RO	Helps user to select the correct programming file.

5.3.5. CvP Status Register

Table 10. CvP Status Register (Byte Offset: 0xB9E)
Bits	Name	Reset Value	Access	Description
[15:11]	—	Variable	RO	Reserved.
[10]	CVP_CONFIG_SUCCESS	Variable	RO	Status bit set by the device to indicate that the core image configuration was successful.
[9]	—	Variable	RO	Reserved.
[8]	PLD_CLK_IN_USE	Variable	RO	From clock switch module to fabric. You can use this bit for debug.
[7]	CVP_CONFIG_DONE	Variable	RO	Indicates that the device has completed the device configuration via CvP and there were no errors.
[6]	—	Variable	RO	Reserved.
[5]	USERMODE	Variable	RO	Indicates if the configurable FPGA fabric is in user mode.
[4]	CVP_EN	Variable	RO	Indicates if the device has enabled CvP mode.
[3]	CVP_CONFIG_ERROR	Variable	RO	Reflects the value of this signal from the device, checked by software to determine if there was an error during configuration.
[2]	CVP_CONFIG_READY	0x0	RO	Reflects the value of this signal from the device, checked by software during programming algorithm to determine the device is ready for configuration.
[1:0]	—	Variable	RO	Reserved.

5.3.6. CvP Mode Control Register

Table 11. CvP Mode Control Register (Byte Offset: 0xBA0)
Bits	Name	Reset Value	Access	Description
[31:3]	—	0x0000	RO	Reserved.
[2]	—	0x0000	RW	Reserved³.
[1]	PLD_DISABLE	1'b0	RW/RO	Enables/disables the PLD interface. This allows Host driver to switch the PLD interface out before USER MODE deasserts, and to switch the PLD interface back in only after USER MODE has been asserted. This helps to prevent any glitches or race conditions during the USER MODE switching. 1: Disable the application layer interface. 0: Enable the application layer interface. Only change the value of this signal when there has been no other TLP’s to or from the HIP for 10 us. There should be no TLP’s issued to the HIP for 10 us after this value changes. When entering CVP, this bit should be set before CVP_MODE is set. When exiting CVP, it should be cleared after CVP_MODE is clears. This ensures that there is no PLD switching during CVP. This field is RW when cvp_en=1, and RO when cvp_en=0.
[0]	CVP_MODE	1'b0	RW	Controls whether the Hard IP for PCI Express is in CVP_MODE or normal mode. 1: CVP_MODE is active. Signals to the SDM active and all TLPs are route to the Configuration Space. This CVP_MODE cannot be enabled if CVP_EN = 0. 0: The IP core is in normal mode and TLPs are route to the FPGA fabric.

³ Intel^® recommends to set the reserved bit to 0 for write operation. For read operations, the PCIe* IP always generates 0 as the output.

5.3.7. CvP Data Registers

Table 12. CvP Data Register (Byte Offsets: 0xBA4 - 0xBA8)
Bits	Name	Reset Value	Access	Description
[31:0]	CVP_DATA	0x00000000	RW	Write the configuration data to this register. The data is transferred to the SDM to configure the device. Software must ensure that all bytes in the memory write dword are enabled. You can access this register using configuration writes. Alternatively, when in CvP mode, this register can also be written by a memory write to any address defined by a memory space BAR for this device. Using memory writes are higher throughput than configuration writes.

5.3.8. CvP Programming Control Register

Table 13. CvP Programming Control Register (Byte Offset: 0xBAC)
Bits	Name	Reset Value	Access	Description
[31:2]	—	0x0000	RO	Reserved.
[1]	START_XFER	1'b0	RW	Sets the CvP output to the FPGA control block indicating the start of a transfer.
[0]	CVP_CONFIG	1'b0	RW	When set to 1, the FPGA control block begins a transfer via CvP.

5.3.9. CvP Credit Register

The credit registers slow down the transmission of the CvP data to handle back pressure when there is no buffer space available within the configuration system. The crediting mechanism handles the back pressure from the configuration system. The total credits register increments each time an additional 4k buffer is available.

Table 14. CvP Credits Register (Byte Offset: 0xBC8)
Bits	Reset Value	Access	Description
[31:16]	0x00	RO	Reserved.
[15:8]	0x00	RO	Least significant 8 bits of the total number of 4k credits granted.
[7:0]	0x00	RO	Reserved.

6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel Stratix 10

6.1. Implementation of CvP Initialization Mode

CvP Initialization mode splits the bitstream into periphery and core images. The periphery image is stored in a local flash device on the PCB. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.

You must specify CvP Initialization mode in the Intel^® Quartus^® Prime Pro Edition software by selecting the CvP Settings Initialization and Update and you must also instantiate the Avalon-ST Intel Stratix 10 Hard IP for PCI Express ⁴.

Figure 8. Example Implementation Flow for CvP Initialization

The CvP Initialization demonstration (based on the Intel^® Stratix^® 10 FPGA Development Kit) walkthrough includes the following steps:

Generating the Synthesis HDL files for Avalon -ST Intel Stratix 10 Hard IP for PCI Express
Setting up the CvP Parameters in Device and Pin Options
Compiling the Design
Converting the SOF File
Bringing up the Hardware

⁴ CvP also supports Avalon^® -MM.

6.1.1. Generating the Synthesis HDL files for Avalon -ST Intel Stratix 10 Hard IP for PCI Express

Follow these steps to generate the synthesis HDL files with CvP enabled:

Open the Intel^® Quartus^® Prime Pro Edition software.
On the Tools menu, click Platform Designer . The Open System window appears.
For System, click + and specify a File Name to create a new platform designer system. Click Create.
On the System Contents tab, delete the clock_in and reset_in components that appear by default.
In the IP Catalog locate and double-click Avalon^® -ST Intel^® Stratix^® 10 Hard IP for PCI Express. The new window appears.
On the IP Settings tab, specify the parameters and options for your design variation.
On the Example Designs tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
For Generated file format, only Verilog is available.
For Target Development Kit, select the board of your choice.
Click the Generate Example Design button. The Select Example Design Directory dialog box appears. Click OK. The software generates Intel^® Quartus^® Prime project files for PCI Express reference design. Click Close when generation completes. An example design pcie_s10_hip_ast_0_example_design is created in your project directory.
Click Finish. Close your current project and open the generated PCI Express example design (pcie_example_design.qpf).
Complete your CvP design by adding any desired top-level design and any other required modules. Pin assignments already being assigned properly based on the target development kit that user specified earlier.

Alternatively, you can download the complete Intel^® Stratix^® 10 CvP Initialization reference design from the link below.

Note: Reference design for CvP update is not available in the current version of the Intel^® Quartus^® Prime software.

6.1.2. Setting up the CvP Parameters in Device and Pin Options

Follow these steps to specify CvP parameters:

On the Intel^® Quartus^® Prime Assignment menu, select Device, and then click Device and Pin Options.
Under Category, select Configuration and then enable the following options:
1. For Configuration scheme, select Active Serial x4(can use Configuration Device).
2. For Use configuration device, select EPCQL1024.
3. For Configuration pin, click Configuration Pin Options and then turn on USE CONF_DONE output and USE CVP_CONFDONE output. Click OK.
  Figure 9. CvP Parameters in Configuration Tab
Under Category, select CvP Settings to specify CvP settings. For Configuration via Protocol, select Initialization and update option. Click OK.
Figure 10. CvP Parameters in CvP Settings Tab
Click OK.

6.1.3. Compiling the Design

To compile the design, on the Processing menu, select Start Compilation to create the .sof file.

6.1.4. Converting the SOF File

Follow these steps to convert your .sof file into separate images for the periphery and core logic.

After the .sof file is generated, under File menu, select Programming File Generator. The new window appears.
In the Device family, select Stratix 10.
For the Configuration mode, select Active Serial x4.
Under Output files tab, specify the following parameters:
1. Specify the Output directory and Name for the output file.
  Note: The output directory you specify must already exist in the file system.
2. Select Raw Binary File for CvP Core Configuration (.rbf).
3. Select JTAG Indirect Configuration File for Periphery Configuration (.jic) if you want to use Active Serial configuration mode.
4. Select Raw Binary File for Periphery Configuration (.rbf) if you want to use AVST configuration mode.
5. Select Memory Map File (.map) or Raw Programming Data File (.rpd) if you plan to use third party programmer for flash programming.
  Figure 11. Programming File Generator- Output Files Tab
Under the Input Files tab, click Add Bitstream. Navigate your file system, and select the .sof file, and click Open.
Figure 12. Programming File Generator- Input Files Tab
Under the Configuration device tab:
1. Click Add Device.
2. Under the Configuration Device tab, click to select your configuration device and click OK.
3. Click to select the configuration device in the list and click Add Partition.
4. In the Add Partition window, select the file in the Input file box, select Start in the Address Mode box, and then click OK.
5. Click Select.
6. In the Select Devices window, click Stratix 10 in the device family list, select your flash loader device in the Device name list, and then click OK.
Figure 13. Programming File Generator- Configuration Device Tab
Click Generate.

6.1.5. Bringing up the Hardware

Before testing the design in hardware, you must install the CvP driver in your DUT system. You can also install RW Utilities or other system verification tools to monitor the link status of the Endpoint and to observe traffic on the link. You can download these utilities for free from many web sites.

Note: You can develop your own custom CvP driver for Linux using the sample Linux driver source code provided by Intel.

The test setup includes the following components:

Intel^® Stratix^® 10 FPGA Development Kit
Intel^® FPGA Download Cable
A DUT PC with PCI Express slot to plug in the FPGA Development Kit
A PC running the Intel^® Quartus^® Prime software to program the periphery image, .sof or .pof file.

6.1.5.1. Installing Open Source CvP Driver in Linux Systems

Download the open source Linux CvP driver from the CvP Driver.
Navigate to the driver directory.
Unzip the drive by typing the following command:
```
tar -zxvf <driver>.gz
```
Run the installation by typing the following command:
```
sudo make
sudo make install
```
Once the installation completed successfully, it generates the altera_cvp file under directory /dev/altera_cvp.

6.1.5.2. Modifying MSEL/DIP switch on Intel Stratix 10 FPGA Development Kit

The MSEL/DIP switch labeled SW1 at the front part of the Intel^® Stratix^® 10 FPGA Development Kit. Select Active Serial x4 (Fast mode) for CvP operation.

Table 15. MSEL Pin Settings for Each Configuration Scheme of Intel^® Stratix^® 10 Devices
Configuration Scheme	MSEL[2:0]
AS (Fast mode - for CvP)⁵	001

⁵ To support AS fast mode, the V_{CCIO_SDM} of Intel^® Stratix^® 10 device must be fully ramped-up within 10ms to the recommended operating conditions. The delay between the device exiting POR and the SDM Boot-up is shorter for the fast mode compared to the normal mode. Therefore, AS fast mode is the recommended configuration scheme for CvP because the device can conform to the PCIe 100ms power-up-to-active time requirement.

6.1.5.3. Programming CvP Images

In Active Serial configuration mode, you must program the periphery image (.periph.jic) into your AS configuration device and then download the core image (.core.rbf) using the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled Intel^® Stratix^® 10 device.

After loading the periphery image, the Intel^® Stratix^® 10 is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Follow these steps to program and test the CvP functionality:

Plug the Intel^® Stratix^® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. It is recommended to use the ATX power supply that the development kit includes.
Open the Intel^® Quartus^® Prime Tools menu and select Programmer.
Click Auto Detect to verify that the Intel^® FPGA Download Cable recognizes the Intel^® Stratix^® 10 FPGA.
Follow these steps to program the periphery image:
1. Select Stratix 10 device, and then right click None under File column and select Change File.
2. Navigate to .periph.jic file and click Open.
3. Under Program/Configure column, select the respective devices. For example, 1SG280LU3S1 and EPCQL1024.
4. Click Start to program the periphery image into EPCQL1024 flash.
Figure 14. Illustrating the Specified Options to the Program Periphery Image
After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel^® Stratix^® 10 FPGA Development Kit.
You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
Follow these steps to program the core image:
1. Copy the .core.rbf file to your working directory.
2. Open a console in Linux. Change the directory to the same mentioned above where the file is copied.
3. Program the core image by typing the following command: cp *.core.rbf /dev/altera_cvp
You can see your core image running on the Intel^® Stratix^® 10 FPGA Development Kit. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.

6.2. Implementation of CvP Update Mode

CvP update mode is a reconfiguration scheme to deliver an updated bitstream to a target device after the device enters user mode.

You must specify this mode in the Intel^® Quartus^® Prime Pro Edition software by selecting the CvP Settings Initialization and Update. The following figure provides the high-level steps for CvP update mode.

Figure 15. Example Implementation Flow for CvP Update

The CvP update mode demonstration walkthrough includes the following steps:

Instantiating the PCIe Hard IP
Setting Up the CvP Parameters
Setting up the Base Revision
Setting up and Compile the Updated Revision
Converting the SOF file of the Updated Revision
Programming the FPGA using the Base Revision Image

6.2.1. Instantiating the PCIe Hard IP

Follow the steps from Generating the Synthesis HDL files for Avalon -ST Intel Stratix 10 Hard IP for PCI Express section to instantiate PCIe* Hard IP and generate the synthesis HDL files with CvP enabled.

6.2.2. Setting Up the CvP Parameters

Specify the CvP parameters in Device and Pin options using the instructions in the Setting up the CvP Parameters in Device and Pin Options section.

6.2.3. Setting up the Base Revision

To set up the base revision, you must create a periphery reuse core partition, define a logic lock region and then compile the base revision. After compilation, you need to export the root partition.

6.2.3.1. Creating a Reserved Core Partition

The following instructions are for creating a reserved core partition from the base revision:

To elaborate the hierarchy of the design, click Processing > Start > Start Analysis & Synthesis.
Right-click an instance in the Project Navigator and click Design Partition > Reserved Core. A design partition icon appears next to each instance you assign.
Figure 16. Creating Design Partition from Project Navigator
This setting corresponds to the following assignment in the .qsf:
```
set_instance_assignment -name PARTITION <name> \
     -to <partition hierarchical path>
```
When defining the partition, select Reserved Core for the partition Type. Ensure that all other partition options are set to default values.
This setting corresponds to the following assignment in the .qsf:
```
set_instance_assignment -name RESERVED CORE ON -to \
     <partition hierarchical path>
```
To export the finalized static region from this base revision compile and to use in subsequent CvP update revision compile, in the Post Final Export File cell, double-click the entry for root_partition and type root_partition.qdb.
Figure 17. Design Partitions Window
This setting corresponds to the following assignment in the .qsf:
```
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \
root_partition -to | -entity top
```

6.2.3.2. Defining a Logic Lock Region

To reserve core resources in an updated revision for the reserved core partition, you must define a fixed size and location, core-only, reserved Logic Lock region. The updated revision uses this area for core development, and the area can contain only core logic. Ensure that the reserved placement region is large enough to contain all core logic in the updated revision.

Follow these steps to define a Logic Lock region for core base revision:

Right-click the design instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears in the Logic Lock Regions Window. You can also verify the region in the Chip Planner (Locate Node > Locate in Chip Planner).

Figure 18. Creating Logic Lock Region from Project Navigator
In the Logic Lock Regions window, specify the Width, Height and the placement region co-ordinates in the Origin column.
Enable the Reserved and Core-Only options.
For Size/State, select Fixed/Locked.
Double-click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.

Figure 19. Logic Lock Regions Window
Specify Fixed with expansion with Expansion Length of 1 for the Routing Type.
Click OK.

Click File > Save Project. This setting corresponds to the following assignment in the .qsf file:

set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to <partition hierarchical path>
set_instance_assignment -name RESERVE_PLACE_REGION ON -to <partition hierarchical path>
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to <partition hierarchical path>
set_instance_assignment -name REGION_NAME led_inst_0 -to <partition hierarchical path>
set_instance_assignment -name ROUTE_REGION "X0 Y0 X21 Y21" -to <partition hierarchical path>
set_instance_assignment -name RESERVE_ROUTE_REGION OFF -to <partition hierarchical path>

6.2.3.3. Compiling and Exporting the Root Partition

To compile the base revision and export the root partition:

To compile the base revision, click Processing > Start Compilation
The base revision provides the exported .qdb file and any optional .sdc files for the periphery reuse core to the new revision.

6.2.4. Setting up and Compile the Updated Revision

In this section, you create a new revision that serves as the updated revision of the base design. The new revision reuses the root partition that is exported from the base revision. However, it uses a new core logic.

Perform the following steps to create and compile an updated revision:

To create a new revision, Click Project > Revisions.
The new Revision window appears. To create a new revision, double-click <<new revision>>. The Create Revision dialog box appears.
Specify the revision name in Revision name field.
For the Based on revision, select the base design, In this example design, the base design is called as top.
Enable This project uses a Partition Database (.qdb) file for the root partition. Browse and add the root_partition.qdb generated from the base design. This setting is also present in the Design Partitions window.
For the Revision Type, select same as top.
Click OK and the Intel^® Quartus^® Prime exist the previous base design and load the new design revision. The new revision opens automatically by Intel^® Quartus^® Prime. You can confirm the current revision opened by the Intel^® Quartus^® Prime through the top tool bar.

Figure 20. Creating Revisions
In the pcie_example_design_update revision, make sure to remove the root_partition.qdb from the Design Partitions Window- Post Final Export File.

Figure 21. Remove root_partition.qdb
Create the new instance or module that you want to replace/update the partition.
Use entity rebinding assignment in design partitions window to change the logic associated with the reserved core partition. Make sure to select the entity rebinding column when you use the entity rebinding assignment

Figure 22. Entity Rebinding Column

For example, First you use green_led as the logic within reserved core partition. Now you change the green_led logic to red_led via entity rebinding, which replaces the green_led instance with a red_led instance.
Figure 23. green_led Entity Re-binding to red_led

Ensure that your Intel^® Quartus^® Prime project top_update includes source files associated with updated Reserved Core partition logic in Intel^® Quartus^® Prime.
In the Intel^® Quartus^® Prime, clickAssignments > Settings > Files and remove the green_led.v file and replace it with red_led.v file.

Verify the following lines in the .qsf file:

set_instance_assignment -name ENTITY_REBINDING red_led -to led_inst_0 -entity top_hw

To run compilation, click Processing > Start Compilation.

6.2.5. Converting the SOF file of the Updated Revision

Follow these steps to convert your .sof file of the updated revision into periphery and core images for CvP update mode.

On the File menu, select Programming File Generator. The new window appears.
In the Device family, select Stratix 10.
For the Configuration mode, select Active Serial x4.
Under Output files tab, specify the following parameters:
1. Specify the Output directory and Name for the output file.
  Note: The output directory you specify must already exist in the file system.
2. Select Raw Binary File for CvP Core Configuration (.rbf).
3. Select JTAG Indirect Configuration File for Periphery Configuration (.jic) if you want to use Active Serial configuration mode.
4. Select Raw Binary File for Periphery Configuration (.rbf) if you want to use AVST configuration mode.
5. Select Memory Map File (.map) or Raw Programming Data File (.rpd) if you plan to use third party programmer for flash programming.
Note: Refer to the Figure 11 .
Under the Input Files tab, click Add Bitstream. Navigate your file system, and select the .sof file, and click Open. Refer to the Figure 12.
Under the Configuration device tab:
1. Click Add Device.
2. Under the Configuration Device tab, click to select your configuration device and click OK.
3. Click to select the configuration device in the list and click Add Partition.
4. In the Add Partition window, select the file in the Input file box, select Start in the Address Mode box, and then click OK.
5. Click Select.
6. In the Select Devices window, click Stratix 10 in the device family list, select your flash loader device in the Device name list, and then click OK.
Note: Refer to the Figure 13.
Click Generate.

6.2.6. Programming the FPGA using the Base Revision Image

For CvP update mode, you must program the FPGA using the base revision image through any configuration scheme. After programming completes the FPGA enters user mode.

The following steps illustrate CvP update on the base revision image programmed through JTAG mode.

Before you begin:

Connect the Intel^® FPGA Download Cable II between your PC USB port and the USB port on the Intel^® Stratix^® 10 FPGA Development Kit.
You must install the altera_cvp driver in your DUT PC system. You can download the open source Linux CvP driver from the CvP Driver.
Note: The Linux driver provided by Intel^® is not a production driver.
Set the MSEL switches of the Intel^® Stratix^® 10 FPGA Development Kit to JTAG mode for CvP update operation.

Follow these steps to program and test CvP update functionality:

Plug the Intel^® Stratix^® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. It is recommended to use the ATX power supply that the development kit includes.
Open the Intel^® Quartus^® Prime Pro Edition software and click Tools > Programmer.
Click Auto Detect to verify that the Intel^® FPGA Download Cable II recognizes the Intel^® Stratix^® 10 FPGA.
Follow these steps to program the base revision .sof file:
1. Select Stratix 10 device, and then right click None under File column and select Change File.
2. Navigate to *.sof file generated from the base revision and click Open.
3. Under Program/Configure column, select the device. For example, 1SG280LU3S1.
4. Click Start. The progress bar reaches 100% when device configuration is complete. The device is fully configured and in operation.
5. After the .sof file is programmed, perform the soft reset on the PC.
6. Once PC has completed soft rebooting, type the following command in a terminal window to make sure the PCIe link is up and running: lspci -vvvd1172.
7. At this time, the FPGA enters into user mode with a functional PCIe link to the DUT PC and you are ready to use the altera_cvp driver to perform the CvP update.
8. Follow these steps to program the core.rbf:
9. Type lspci -vvvd1172 in a terminal window to make sure that you have an active PCIe link.
10. Program the core.rbf generated from the updated revision by typing the following command:
```
dd if= <new core.rbf file> of= /dev/altera_cvp bs=4K
```
  Sample output:
```
<hostname># dd if=top.core.cvpinit.19p3.rbf of=/dev/altera_cvp bs=4K
981+0 records in
981+0 records out
4018176 bytes (4.0 MB) copied, 0.348371 s, 11.5 MB/s
```

7. Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

Quartus Version	User Guide
18.1	Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide
18.0	Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide
17.1	Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide

8. Document Revision History

Table 16. Document Revision History for Intel^® Stratix^® 10 Configuration via Protocol Implementation User Guide
Document Version	Intel^® Quartus^® Prime Version	Changes
2021.02.19	19.3	Sections updated: CvP Modes CvP System Configuration Images
2020.09.22	19.3	Removed support for Avalon^® Streaming (Avalon-ST) x8 configuration scheme. Added a note in section CvP Systems to clarify the location of the PCIe* Hard IP block. Added information about the supported tile in Table: CvP Support for Intel^® Stratix^® 10 Device Family.
2020.05.19	19.3	Corrected the file selection for AVST configuration mode in the following sections: Converting the SOF File Converting the SOF file of the Updated Revision
2020.01.10	19.3	Updated Figure: PCIe Timing Sequence in CvP Initialization Mode to include GPIO status.
2019.12.16	19.3	Added a link to the Intel Stratix 10 CvP Update Reference Design. Updated following links: CvP driver link Intel Stratix 10 CvP Initialization Reference Design Modified the steps in the following sections: Creating a Reserved Core Partition Setting up and Compile the Updated Revision Added information about checking the .qsf file settings in Defining a Logic Lock Region section. Modified step tp program the core.rbf file in section Programming the FPGA using the Base Revision Image.
2019.09.30	19.3	Added support for Avalon^® Streaming x8 configuration scheme. Replaced the Convert Programming File (CPF) tool related information with Programming File Generator (PFG) in the following sections: Converting the SOF File Converting the SOF File of the Updated Revision
2019.07.26	18.1	Corrected the byte offset for the CvP Programming Control Register. Corrected register name in Figure 7: CvP Driver Flow.
2019.06.20	18.1	Clarified how to program the FPGA for CvP update mode.
2019.01.17	18.1	Modified the following in Setting up the Base Revision section: Figure: Creating Design Partition from Project Navigator Figure: Design Partitions Window Figure: Creating Logic Lock Region from Project Navigator Added Figure: Design Partitions Window in section Setting up and Compile the Updated Revision section.
2018.11.29	18.1	Modified the following diagrams: Figure: Single Endpoint Topology Figure: Multiple Endpoints Topology
2018.09.24	18.1	CvP update mode is now supported in the current version of the Intel^® Quartus^® Prime Pro Edition software. Added new section Implementation of CvP Update Mode. Modified diagrams: Figure: Periphery and Core Image Storage Arrangement for CvP Core Image Update Figure: Single Endpoint Topology Figure: Multiple Endpoints Topology Updated Figure: CvP Driver Flow in section CvP Driver Flow. `CVP_DATA2` register is no longer functional in Intel^® Stratix^® 10 devices. Added new sections: CvP Limitations and Restrictions CvP Error Recovery Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide Archives
2018.07.17	18.0	Added a note in CvP Modes section to clarify CvP update mode support in the current version of the Intel^® Quartus^® Prime Pro Edition software. Modified Figure: PCIe Timing Sequence in CvP Initialization Mode diagram.
2018.06.18	18.0	Corrected the periphery image and core image definitions in Configuration Images section. Added Figure: PCIe Timing Sequence in CvP Initialization Mode diagram and Table: Power-up Sequence Timing in CvP Initialization Mode information for CvP initialization. Modified Figure: Single Endpoint Topology and Figure: Multiple Endpoint Topology in CvP Topologies chapter. Added a note to clarify the Linux driver support provided by Intel^® . Updated the Figure: CvP Driver Flow. Corrected the VSEC registers for CvP in VSEC Registers for CvP section. Minor updates in Implementation of CvP Initialization Mode section.

Date	Version	Changes
December 2017	2017.12.18	Initial release.