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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Altera Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
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1.2. CvP System
A CvP system typically consists of an FPGA, a PCIe* host, and a configuration device.
Figure 1. CvP Block Diagram for Agilex™ 5 FPGA
- The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme.
- The PCIe* Hard IP blocks located near the SDM block are on the left side and can be used for CvP applications, however, only one can be used for CvP application at a time.
- PCIe* Hard IP blocks that are not used for CvP can be used for PCIe* application.
Note: For PCIe* design including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe* wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enter link training state before PERST# deasserted.