Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents

7.2.4. JTAG Configuration

In Intel® Cyclone® 10 GX devices, JTAG instructions take precedence over other configuration schemes.

The Quartus® Prime Pro Edition software generates an SRAM Object File (.sof) that you can use for JTAG configuration using a download cable in the Quartus® Prime Pro Edition software programmer. Alternatively, you can use the JRunner software with .rbf or a JAM™ Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte Code File (.jbc) with other third-party programmer tools.

Note: You cannot use the Intel® Cyclone® 10 GX decompression or design security features if you are configuring your Intel® Cyclone® 10 GX device using JTAG-based configuration.

The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Intel® Cyclone® 10 GX devices do not affect JTAG boundary-scan or programming operations.

The Intel FPGA download cable can support VCCPGM supply at 1.5 V or 1.8 V; it does not support a target supply voltage of 1.2 V.

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