Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11

The following timing diagram shows the requirement of the IP core to access the voltage sensor in the core access mode when MD[1:0] is equal to 2'b11.

Timing Diagram when MD[1:0] is Equal to 2'b11


  1. Low-to-high transition for the corectl signal enables the core access mode.
    1. Wait for a minimum of two clock pulses before proceeding to step 2.
  2. De-asserting the reset signal releases the voltage sensor from the reset state.
    1. Wait for a minimum two clock pulses before proceeding to step 3.
  3. Configure the voltage sensor by writing into the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register for the core access mode is 8-bit wide and configuration data is shifted in serially into the configuration register.
  4. Specify the channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal needs to be ready before the coreconfig signal is de-asserted.
  5. The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register and the chsel[3:0] signal.
  6. Specify the next channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal needs to be ready one cycle before the eoc signal asserts. Poll the eoc and eos status signals to check if conversion for the first channel defined by the chsel[3:0] signal in step 4 is completed. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
  7. Repeat step 6 for all the subsequent channels.

Did you find the information on this page useful?

Characters remaining:

Feedback Message